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[83.6.170.196]) by smtp.googlemail.com with ESMTPSA id g144sm5671179wme.2.2020.06.23.15.48.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2020 15:48:38 -0700 (PDT) From: Konrad Dybcio To: skrzynka@konradybcio.pl Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 08/12] arm64: dts: qcom: msm8994: Add pmu node Date: Wed, 24 Jun 2020 00:48:07 +0200 Message-Id: <20200623224813.297077-9-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200623224813.297077-1-konradybcio@gmail.com> References: <20200623224813.297077-1-konradybcio@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the CPU PMU to get perf support for hardware events. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 8af01ebe73f7..b3c01ebc5c67 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -154,6 +154,11 @@ memory { reg = <0 0 0 0>; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; -- 2.27.0