Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp599301ybt; Wed, 24 Jun 2020 06:52:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJygLYypopMUT3UGkqT9PX5xuM5BkwXHTCLPtovCQTPo4JKjalYiL8TUXh2w64k4jS7YwFNJ X-Received: by 2002:a17:906:17d5:: with SMTP id u21mr3307534eje.413.1593006745509; Wed, 24 Jun 2020 06:52:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593006745; cv=none; d=google.com; s=arc-20160816; b=AOmNnw/yIMqYo+owu0VbX2HK9yBOufQPAAYBBefV34JHSPWG9X2rTp3wm3YE4UH3xH GZs1mmjEb2EAbIaKvDKf1fy39SNm/qAS9ZAdCQIZDsn68PhQtQrkDm85jjxioXQvq14W mJ55kCZZSXJSrw3CmXOpyPc/My3rHs+GvZE8CzJe66UhrahBQSSHxDkUhQr+M4xItq4/ O6GtYgXw92LFgoWT7dFM1Cw0yXC0Jtj5d+NMNruHqiz4mGxVHLTAl4AprfnEOQlF4K68 SPjZkBiPHwpT1Yevj/IRidCulfD01KINosOTVg8zasFiFDLbzU+U51tGBAXM765XvfiH 3gBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:cc:to:subject :message-id:date:from:in-reply-to:references:mime-version :dkim-signature; bh=HMgVoQ0NH17cOLvd+EMrZ4qMVzF5NeVckkBSBDB5GLs=; b=uO9EP4IngHA1l1aaBxu6RwruqPwjcMQwK1VLuy4C1+tXk3l3cdXSIcg/qO/qeQyzC7 WW1oj+9/kQeGeji5JABf4EtPgAfK0cgY52cDw6YfWpbATVVHr6LPmKc5VQAWqc3FGQ3k SwUap26GYnjGxy+5+Josa2hqHi6hy2NNUhXF6RqMpRkuuY//xEvHsa0X/9cbZUfZ5XzJ JeH1o52KykhPVqPYSmQoZEipsj4zbJANXeS2x3p4kzADmXzYZEmBxQMYGcAdtcmrfvVV Z0ImGNuKjURUfdLdPc72dRqPm3lIGHeixkIVL6VRmcdpJcCWxNaLaRyW3vgnIBWZ1pN7 BTnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20150623.gappssmtp.com header.s=20150623 header.b=0jvmCkm1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id f9si15659044ejl.52.2020.06.24.06.52.00; Wed, 24 Jun 2020 06:52:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20150623.gappssmtp.com header.s=20150623 header.b=0jvmCkm1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391117AbgFXNtF (ORCPT + 99 others); Wed, 24 Jun 2020 09:49:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391102AbgFXNtB (ORCPT ); Wed, 24 Jun 2020 09:49:01 -0400 Received: from mail-il1-x144.google.com (mail-il1-x144.google.com [IPv6:2607:f8b0:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A19A8C061573 for ; Wed, 24 Jun 2020 06:49:01 -0700 (PDT) Received: by mail-il1-x144.google.com with SMTP id z2so2136896ilq.0 for ; Wed, 24 Jun 2020 06:49:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=HMgVoQ0NH17cOLvd+EMrZ4qMVzF5NeVckkBSBDB5GLs=; b=0jvmCkm1uxOa1uyi4BAYlDRMMqRDa38wgi9E8/XIDdGrA9oQ5L4spIW2A1eGA4BtF2 S8zElmWx4UIeuMFNfhPYYnWZuScbEVueJuWuV4FXywiqce4LL2run2a4ymvcOzIu/C/+ 6Fe7gIuaYQNI6sGKgF4WgNb2BUsmVdRrHfRKrtAsfldLg5IvcbHl6PWauCZhmFQojQhm 9a7Q5RrPl/lbr4+33xEC9+RPw7xZD15uxySVT5i1FJFwQookYTDkrFsYT0wH0jVU3Rlu L9Tp3z1r1c62MEmeG50kWokbFvxn6cOtU/lGUbjrNM0wFfDadl3nZISJG+6IalJfMcDf 33mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=HMgVoQ0NH17cOLvd+EMrZ4qMVzF5NeVckkBSBDB5GLs=; b=UhQOk5MbUGWm3JtRytqindywQIGmjd2xlqya67ROJQgRfumpGmFWe8GFCaC/0jkWcd kBSLhwF6Ss1dkt6zcPRNi4tYi9vt90RBob7Kgy44oiUrXsdbBt9E+7evS1MaKeGa53eZ UK7IxnH2gqKbtWEtRsC1orDKG6B3DVFVoKaaskpN+POEjo6qR1lnMShlQOz2CIX2642h u7C1djOUWxsOuzC037ZR3U0C0CtfKWQfuLtLcqqUUG7SMD5And8NgH+ZE1cQIPPc3Wa+ 2SuqLqd16bQCRuIODorsXsWuVE7s8RWxmPEvyKS5E7XmIA2HDiCsIG8Nc6tamwlmJUbV g6Qg== X-Gm-Message-State: AOAM533+UCmECAAuQrkmJemMHThhF8qfhyvMbTfi1lZlWD0MTODPna18 0F4bMEzZVOkBdN1uYSFVaBQ7uyCpFMv9BkjLnHy6SQ== X-Received: by 2002:a92:de10:: with SMTP id x16mr29799293ilm.6.1593006540971; Wed, 24 Jun 2020 06:49:00 -0700 (PDT) MIME-Version: 1.0 References: <20200622093744.13685-1-brgl@bgdev.pl> <20200622093744.13685-10-brgl@bgdev.pl> <20200622133940.GL338481@lunn.ch> <20200622135106.GK4560@sirena.org.uk> <20200624094302.GA5472@sirena.org.uk> In-Reply-To: <20200624094302.GA5472@sirena.org.uk> From: Bartosz Golaszewski Date: Wed, 24 Jun 2020 15:48:50 +0200 Message-ID: Subject: Re: [PATCH 09/15] net: phy: delay PHY driver probe until PHY registration To: Mark Brown Cc: Florian Fainelli , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Rob Herring , Matthias Brugger , Microchip Linux Driver Support , Vladimir Oltean , Claudiu Manoil , Alexandre Belloni , Vivien Didelot , Tom Lendacky , Yisen Zhuang , Salil Mehta , Jassi Brar , Ilias Apalodimas , Iyappan Subramanian , Keyur Chudgar , Quan Nguyen , Frank Rowand , Philipp Zabel , Liam Girdwood , netdev , devicetree , Linux Kernel Mailing List , Linux ARM , "moderated list:ARM/Mediatek SoC..." , Fabien Parent , Stephane Le Provost , Pedro Tsai , Andrew Perepech , Bartosz Golaszewski Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org =C5=9Br., 24 cze 2020 o 11:43 Mark Brown napisa=C5=82(= a): > > On Tue, Jun 23, 2020 at 12:49:15PM -0700, Florian Fainelli wrote: > > On 6/22/20 6:51 AM, Mark Brown wrote: > > > > If the bus includes power management for the devices on the bus the > > > controller is generally responsible for that rather than the devices, > > > the devices access this via facilities provided by the bus if needed. > > > If the device is enumerated by firmware prior to being physically > > > enumerable then the bus will generally instantiate the device model > > > device and then arrange to wait for the physical device to appear and > > > get joined up with the device model device, typically in such situati= ons > > > the physical device might appear and disappear dynamically at runtime > > > based on what the driver is doing anyway. > > > In premise there is nothing that prevents the MDIO bus from taking care > > of the regulators, resets, prior to probing the PHY driver, what is > > complicated here is that we do need to issue a read of the actual PHY t= o > > know its 32-bit unique identifier and match it with an appropriate > > driver. The way that we have worked around this with if you do not wish > > such a hardware access to be made, is to provide an Ethernet PHY node > > compatible string that encodes that 32-bit OUI directly. In premise the > > same challenges exist with PCI devices/endpoints as well as USB, would > > they have reset or regulator typically attached to them. > > That all sounds very normal and is covered by both cases I describe? > > > > We could use a pre-probe stage in the device model for hotpluggable > > > buses in embedded contexts where you might need to bring things out o= f > > > reset or power them up before they'll appear on the bus for enumerati= on > > > but buses have mostly handled that at their level. > > > That sounds like a better solution, are there any subsystems currently > > implementing that, or would this be a generic Linux device driver model > > addition that needs to be done? > > Like I say I'm suggesting doing something at the device model level. I didn't expect to open such a can of worms... This has evolved into several new concepts being proposed vs my use-case which is relatively simple. The former will probably take several months of development, reviews and discussions and it will block supporting the phy supply on pumpkin boards upstream. I would prefer not to redo what other MAC drivers do (phy-supply property on the MAC node, controlling it from the MAC driver itself) if we've already established it's wrong. Is there any compromise we could reach to add support for a basic, common use-case of a single regulator supplying a PHY that needs enabling before reading its ID short-term (just like we currently support a single reset or reset-gpios property for PHYs) and introducing a whole new concept to the device model for more advanced (but currently mostly hypothetical) cases long-term? Bart