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Thu, 25 Jun 2020 23:13:25 +0000 From: Krishna Reddy To: Thierry Reding CC: Sachin Nikam , Mikko Perttunen , Bryan Huntsman , "will@kernel.org" , "joro@8bytes.org" , "linux-kernel@vger.kernel.org" , Pritesh Raithatha , Timo Alho , "iommu@lists.linux-foundation.org" , Nicolin Chen , "linux-tegra@vger.kernel.org" , Yu-Huan Hsu , Thierry Reding , "robin.murphy@arm.com" , "linux-arm-kernel@lists.infradead.org" , Bitan Biswas Subject: RE: [PATCH v6 1/4] iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage Thread-Topic: [PATCH v6 1/4] iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage Thread-Index: AQHWOsoZSFzbl7gVUU+vg5iuyN0v3KjmHMOAgAP6GSA= Date: Thu, 25 Jun 2020 23:13:24 +0000 Message-ID: References: <20200604234414.21912-1-vdumpa@nvidia.com> <20200604234414.21912-2-vdumpa@nvidia.com> <20200623102927.GD4098287@ulmo> In-Reply-To: <20200623102927.GD4098287@ulmo> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_6b558183-044c-4105-8d9c-cea02a2a3d86_Enabled=True; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1593126798; bh=SXr0IHT5rfZ8A7MBA7j/Q5vR7/xdmEVEkrWGT0ocueo=; h=X-PGP-Universal:ARC-Seal:ARC-Message-Signature: ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic: Thread-Index:Date:Message-ID:References:In-Reply-To: Accept-Language:X-MS-Has-Attach:X-MS-TNEF-Correlator:msip_labels: authentication-results:x-originating-ip:x-ms-publictraffictype: x-ms-office365-filtering-correlation-id:x-ms-traffictypediagnostic: x-ms-exchange-transport-forked:x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers:x-forefront-prvs: x-ms-exchange-senderadcheck:x-microsoft-antispam: x-microsoft-antispam-message-info:x-forefront-antispam-report: x-ms-exchange-antispam-messagedata:MIME-Version: X-MS-Exchange-CrossTenant-AuthAs: X-MS-Exchange-CrossTenant-AuthSource: X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-CrossTenant-userprincipalname: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg: Content-Language:Content-Type:Content-Transfer-Encoding; b=fFQJx0L9LVajnSRDPZ3VLLZ7eS/rzw/3gNmqv5DwgGww9Raq8fHHn0HtV26uuFRNy Ww+d2bxibOutbAgmY7NaJJ8UGrlVIVpWhrch5t7b4G+ix1IBNOYuIBmzh0mpLORNKm 1IVDl2j8xxoZKxPAbJIkzMu8r8xZ2XoRgA8NjGkSxsQE+7ibouxUqJRxqgaHWgCLtC 74ovanIJe2MLI0MD27dE9kx6oZniKzNkrjGB6UZkcmJzBjPuVbLQapP8CcLp6m2KVW blFafXkg/OhF5sS15PodY5wdy+mvQPQl8gxXXkctWHBS+RrTCLj8k+g3GeyeqU27x7 eT5qivaSpzcaw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >Should NVIDIA_TEGRA194_SMMU be a separate value for smmu->model, perhaps? = That way we avoid this somewhat odd check here. NVIDIA haven't made any changes to arm,mmu-500. It is only used in differen= t topology. New model would be mis-leading here. As suggested by Robin, It can just be moved to end of function. >> diff --git a/drivers/iommu/arm-smmu-nvidia.c=20 >> b/drivers/iommu/arm-smmu-nvidia.c >I wonder if it would be better to name this arm-smmu-tegra.c to make it cl= earer that this is for a Tegra chip. We do have regular expressions in MAIN= TAINERS that catch anything with "tegra" in it to make this easier. >Also, the nsmmu_ prefix looks somewhat odd here. You already use struct nv= idia_smmu as the name of the structure, so why not be consistent and contin= ue to use nvidia_smmu_ as the prefix for function names? >Or perhaps even use tegra_smmu_ as the prefix to match the filename change= I suggested earlier. Prefix can be updated to nvidia_smmu as we seem to be okay for now to keep = file name as arm-smmu-nvidia.c after the vendor name. =20 >> +#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ >USEC_PER_SEC? It is not meant for a conversion. Reused Timeout variable from arm-smmu.c f= or tlb_sync implementation. Can rename it to TLB_LOOP_TIMEOUT_IN_US. >> + } >> + dev_err_ratelimited(smmu->dev, >> + "TLB sync timed out -- SMMU may be deadlocked\n"); >Same here. >Also, is there anything we can do when this happens? This is never expected to happen on Silicon. This code and message is reuse= d from arm-smmu.c. >> +#define nsmmu_page(smmu, inst, page) \ >> + (((inst) ? to_nvidia_smmu(smmu)->bases[(inst)] : smmu->base) + \ >> + ((page) << smmu->pgshift)) >Can we simply define to_nvidia_smmu(smmu)->bases[0] =3D smmu->base in nvid= ia_smmu_impl_init()? Then this would become just: > to_nvidia_smmu(smmu)->bases[inst] + ((page) << (smmu)->pgshift) > + >Maybe add this here to simplify the nsmmu_page() macro above: > nsmmu->bases[0] =3D smmu->base; This preferred to avoid the check in nsmmu_page(). But, smmu->base is not y= et populated when nvidia_smmu_impl_init() is called. =20 Let me look at the alternative place to set it. -KR