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Sun, 28 Jun 2020 05:05:15 +0000 From: Andy Duan To: Sven Van Asbroeck , "shawnguo@kernel.org" CC: Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , dl-linux-imx , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: RE: [EXT] [PATCH v4 2/2] ARM: imx6plus: enable internal routing of clk_enet_ref where possible Thread-Topic: [EXT] [PATCH v4 2/2] ARM: imx6plus: enable internal routing of clk_enet_ref where possible Thread-Index: AQHWSvkYcUowKEcmtU6JLU1iKnAQWajtfTlQ Date: Sun, 28 Jun 2020 05:05:15 +0000 Message-ID: References: <20200625140105.14999-1-TheSven73@gmail.com> <20200625140105.14999-2-TheSven73@gmail.com> In-Reply-To: <20200625140105.14999-2-TheSven73@gmail.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=none action=none header.from=nxp.com; x-originating-ip: [119.31.174.68] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 5c155350-6b8d-4a8e-15ef-08d81b20d878 x-ms-traffictypediagnostic: AM6PR0402MB3605: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5797; 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x-ms-exchange-antispam-messagedata: 7Fa5VLbx32Ct+wFoAa2hOSvGBGGFthzSWXxHzTnMYvueBB/kdRZM5v7vss7JaDvAsHkXfH646Ufg4U6vgU84sUFm0exV36ZvSp9yjiUwkdWM6yqO0zLOSLy88TDlF1WjdZ9n0lKjrTyZmj4fcA0gzmi3J+60Z9kk+mqEFy2unXT+0aBD+KtDCi/Q4d67NEKx+zbzvOHiipe/I/3jLjIqJphkJLIrcuN/u94VPB5vX68UxecsNcThNVunl7moSO/GDGs3egYC07g4+rmSpNlIDifDNQWTyBwFpOgTUS83etaka2J2Ktb9xHfPt87tHc6LttUulXG/Cv2aRyZIdqotNIK5SSEOCBrrs0G1P9vAQkJilfbMU8taCnjKskr17J/5PFVnoWCKh/NeyCTb8pGFjoh4wWfcEohDoZo55avdoCkE6o+F0kVtWL9+4MbmN4GoLaAnfRL5PDOf++TeQCOjborNBMvoHzhhPw2lJWuvxJs= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM6PR0402MB3607.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5c155350-6b8d-4a8e-15ef-08d81b20d878 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Jun 2020 05:05:15.6439 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ySbnv1FMsmGCO8zgRDe6TSMePnvmgT6z/FAgssPkR+vB91YgHVO6/v8M1TTi4YQPwduBw022/sAxdQet6eJdEw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0402MB3605 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sven Van Asbroeck Sent: Thursday, June 25, 2020= 10:01 PM > On imx6, the ethernet reference clock (clk_enet_ref) can be generated by > either the imx6, or an external source (e.g. an oscillator or the PHY). W= hen > generated by the imx6, the clock source (from ANATOP) must be routed to t= he > input of clk_enet_ref via two pads on the SoC, typically via a dedicated = track > on the PCB. >=20 > On an imx6 plus however, there is a new setting which enables this clock = to > be routed internally on the SoC, from its ANATOP clock source, straight t= o > clk_enet_ref, without having to go through the SoC pads. >=20 > Board designs where the clock is generated by the imx6 should not be > affected by routing the clock internally. Therefore on a plus, we can ena= ble > internal routing by default. >=20 > Signed-off-by: Sven Van Asbroeck For the version: Reviewed-by: Fugang Duan > --- > v3 -> v4: > - avoid double-check for IS_ERR(gpr) by including Fabio Estevam's > patch. > v2 -> v3: > - remove check for imx6q, which is already implied when > of_machine_is_compatible("fsl,imx6qp") > v1 -> v2: > - Fabio Estevam: use of_machine_is_compatible() to determine if we > are running on an imx6 plus. >=20 > To: Shawn Guo > To: Andy Duan > Cc: Sascha Hauer > Cc: Pengutronix Kernel Team > Cc: Fabio Estevam > Cc: NXP Linux Team > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org >=20 > arch/arm/mach-imx/mach-imx6q.c | 14 ++++++++++++++ > include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + > 2 files changed, 15 insertions(+) >=20 > diff --git a/arch/arm/mach-imx/mach-imx6q.c > b/arch/arm/mach-imx/mach-imx6q.c index ae89ad93ca83..07cfe0d349c3 > 100644 > --- a/arch/arm/mach-imx/mach-imx6q.c > +++ b/arch/arm/mach-imx/mach-imx6q.c > @@ -204,6 +204,20 @@ static void __init imx6q_1588_init(void) > regmap_update_bits(gpr, IOMUXC_GPR1, > IMX6Q_GPR1_ENET_CLK_SEL_MASK, > clksel); >=20 > + /* > + * On imx6 plus, enet_ref from ANATOP/CCM can be internally > routed to > + * be the PTP clock source, instead of having to be routed throug= h > + * pads. > + * Board designs which route the ANATOP/CCM clock through pads > are > + * unaffected when routing happens internally. So on these design= s, > + * route internally by default. > + */ > + if (clksel =3D=3D IMX6Q_GPR1_ENET_CLK_SEL_ANATOP && > + of_machine_is_compatible("fsl,imx6qp")) > + regmap_update_bits(gpr, IOMUXC_GPR5, > + IMX6Q_GPR5_ENET_TXCLK_SEL, > + IMX6Q_GPR5_ENET_TXCLK_SEL); > + > clk_put(enet_ref); > put_ptp_clk: > clk_put(ptp_clk); > diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > index d4b5e527a7a3..eb65d48da0df 100644 > --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > @@ -240,6 +240,7 @@ > #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) >=20 > #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) > +#define IMX6Q_GPR5_ENET_TXCLK_SEL BIT(9) > #define IMX6Q_GPR5_SATA_SW_PD BIT(10) > #define IMX6Q_GPR5_SATA_SW_RST BIT(11) >=20 > -- > 2.17.1