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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id j70sm12876254pfd.208.2020.06.28.20.19.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 20:19:29 -0700 (PDT) From: Zong Li To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [RFC PATCH 6/6] riscv: remove PMU menu of Kconfig Date: Mon, 29 Jun 2020 11:19:15 +0800 Message-Id: X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We only one instance of riscv_pmu now, and use DT file to describe the platform-specific information, so drop the dependency and menu of RISCV_BASE_PMU. Signed-off-by: Zong Li --- arch/riscv/Kconfig | 13 ------------- arch/riscv/include/asm/perf_event.h | 2 -- arch/riscv/kernel/Makefile | 2 +- 3 files changed, 1 insertion(+), 16 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 128192e14ff2..deec11e924ce 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -292,19 +292,6 @@ config RISCV_ISA_C If you don't know what to do here, say Y. -menu "supported PMU type" - depends on PERF_EVENTS - -config RISCV_BASE_PMU - bool "Base Performance Monitoring Unit" - def_bool y - help - A base PMU that serves as a reference implementation and has limited - feature of perf. It can run on any RISC-V machines so serves as the - fallback, but this option can also be disable to reduce kernel size. - -endmenu - config FPU bool "FPU support" default y diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h index e95d3bbaae3e..9ee654381d8c 100644 --- a/arch/riscv/include/asm/perf_event.h +++ b/arch/riscv/include/asm/perf_event.h @@ -12,7 +12,6 @@ #include #include -#ifdef CONFIG_RISCV_BASE_PMU #define RISCV_BASE_COUNTERS 2 #define RISCV_EVENT_COUNTERS 29 #define RISCV_TOTAL_COUNTERS (RISCV_BASE_COUNTERS + RISCV_EVENT_COUNTERS) @@ -79,7 +78,6 @@ #define CSR_MHPMEVENT7 0x327 #define CSR_MHPMEVENT8 0x328 -#endif #ifdef CONFIG_PERF_EVENTS #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs #endif diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index b355cf485671..1f5736e996fd 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -43,7 +43,7 @@ obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o -obj-$(CONFIG_RISCV_BASE_PMU) += perf_event.o +obj-$(CONFIG_PERF_EVENTS) += perf_event.o obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o obj-$(CONFIG_RISCV_SBI) += sbi.o -- 2.27.0