Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp2973944ybt; Mon, 29 Jun 2020 11:52:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxFzpnpWN7KOBrDr+bmwnbQ9bVm0ihDdSjtVNO7AcM8cCfgizG1isrtkA4DCXdPUpGsyz/E X-Received: by 2002:a17:907:1002:: with SMTP id ox2mr14916534ejb.358.1593456749945; Mon, 29 Jun 2020 11:52:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593456749; cv=none; d=google.com; s=arc-20160816; b=CIFvUEm+LwW5UsVRkfVX/rAA6PHRLIQTwby4fdoyN31hlTVbcDaFX1l/K8o/uqtRhU Vh+5MTpzX63mQbuJPWAsuK6w6UoQ4x2w2Q0KBnobwMzfR2gy3XLJzOc6MSwDxoN9sdGk FKIRfwnOh4l7HavYMGqWb8uiJmh5UykXabgA34AURCeemdwMyhUb+uHX/LwhEqOvVUua GnHnEs4FUjT0t4YU5+gHAawgL8CT9DqSulGE0myQKmpYOR3bGEfdEBIGdkvKVPptk1xO xi0ClqpaoRY/b1FRs3TDOK6FX/g8QudRsEMqsKbKJM3Rzvittn36xU9SSUHwimMjfO4O 1IAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject; bh=dJzDsB52ElO4jEWdf6SM1xbzdKRo315w1VrPeGpbjVY=; b=cGeSOJyonrKiIyCRgUOwdr2H9TrJeGEARtG6xdSfbvnHiiuhZHFY9gJkEPPlWDsie7 XuK8/UyBOJgv6Jscy/hjcyFZhD2VwuyL+xdeuiZccS+kMW3Fwu9r2+Pwe1PmqwcBt9yD pGIueDSsOt/yJDxVb73RrdfUpUG+VrOencH9dDVXnRZutOPI9iu/p10sL1vpPGAIZYEy bGCrZSMULNzat8gubuCkVFIwUy6f0wt914NWHV3JSr0lBQXzfnCJIlr9ocygxFQzAVBe YQxATn3WZWfS9EHjfeBPHoQJLy6IzBZRWEzBWgjrLsW6cZNSZvuHqycbhO0Bss1muy2P beFg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a2si199891edq.272.2020.06.29.11.52.06; Mon, 29 Jun 2020 11:52:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728065AbgF2SuI (ORCPT + 99 others); Mon, 29 Jun 2020 14:50:08 -0400 Received: from foss.arm.com ([217.140.110.172]:36234 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729000AbgF2SuA (ORCPT ); Mon, 29 Jun 2020 14:50:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 125D91435; Mon, 29 Jun 2020 04:41:59 -0700 (PDT) Received: from [10.37.12.67] (unknown [10.37.12.67]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5DA9D3F73C; Mon, 29 Jun 2020 04:41:56 -0700 (PDT) Subject: Re: brocken devfreq simple_ondemand for Odroid XU3/4? To: Sylwester Nawrocki Cc: Krzysztof Kozlowski , Willy Wolff , Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Kukjin Kim , linux-pm@vger.kernel.org, "linux-samsung-soc@vger.kernel.org" , linux-arm-kernel@lists.infradead.org, "linux-kernel@vger.kernel.org" References: <20200623164733.qbhua7b6cg2umafj@macmini.local> <20200623191129.GA4171@kozik-lap> <85f5a8c0-7d48-f2cd-3385-c56d662f2c88@arm.com> <4a72fcab-e8da-8323-1fbe-98a6a4b3e0f1@arm.com> <708feba7-6b11-4943-1073-a1b5e54b6283@samsung.com> From: Lukasz Luba Message-ID: Date: Mon, 29 Jun 2020 12:41:54 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <708feba7-6b11-4943-1073-a1b5e54b6283@samsung.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/26/20 6:50 PM, Sylwester Nawrocki wrote: > Hi Lukasz, > > On 25.06.2020 12:02, Lukasz Luba wrote: >> Regarding the 'performance counters overflow interrupts' there is one >> thing worth to keep in mind: variable utilization and frequency. >> For example, in order to make a conclusion in algorithm deciding that >> the device should increase or decrease the frequency, we fix the period >> of observation, i.e. to 500ms. That can cause the long delay if the >> utilization of the device suddenly drops. For example we set an >> overflow threshold to value i.e. 1000 and we know that at 1000MHz >> and full utilization (100%) the counter will reach that threshold >> after 500ms (which we want, because we don't want too many interrupts >> per sec). What if suddenly utilization drops to 2% (i.e. from 5GB/s >> to 250MB/s (what if it drops to 25MB/s?!)), the counter will reach the >> threshold after 50*500ms = 25s. It is impossible just for the counters >> to predict next utilization and adjust the threshold. > > Agreed, that's in case when we use just the performance counter (PMCNT) > overflow interrupts. In my experiments I used the (total) cycle counter > (CCNT) overflow interrupts. As that counter is clocked with fixed rate > between devfreq updates it can be used as a timer by pre-loading it with > initial value depending on current bus frequency. But we could as well > use some reliable system timer mechanism to generate periodic events. > I was hoping to use the cycle counter to generate low frequency monitor > events and the actual performance counters overflow interrupts to detect > any sudden changes of utilization. However, it seems it cannot be done > with as simple performance counters HW architecture as on Exynos4412. > It looks like on Exynos5422 we have all what is needed, there is more > flexibility in selecting the counter source signal, e.g. each counter > can be a clock cycle counter or can count various bus events related to > actual utilization. Moreover, we could configure the counter gating period > and alarm interrupts are available for when the counter value drops below > configured MIN threshold or exceeds configured MAX value. I see. I don't have TRM for Exynos5422 so couldn't see that. I also have to keep in mind other platforms which might not have this feature. > > So it should be possible to configure the HW to generate the utilization > monitoring events without excessive continuous CPU intervention. I agree, that would be desirable especially for low load in the system. > But I'm rather not going to work on the Exynos5422 SoC support at the moment. I see. > >> To address that, we still need to have another mechanism (like watchdog) >> which will be triggered just to check if the threshold needs adjustment. >> This mechanism can be a local timer in the driver or a framework >> timer running kind of 'for loop' on all this type of devices (like >> the scheduled workqueue). In both cases in the system there will be >> interrupts, timers (even at workqueues) and scheduling. >> The approach to force developers to implement their local watchdog >> timers (or workqueues) in drivers is IMHO wrong and that's why we have >> frameworks. > > Yes, it should be also possible in the framework to use the counter alarm > events where the hardware is advanced enough, in order to avoid excessive > SW polling. Looks promising, but that would need more plumbing I assume. Regards, Lukasz > > -- > Regards, > Sylwester >