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From:   Baolin Wang <baolin.wang7@gmail.com>
Date:   Mon, 29 Jun 2020 22:35:06 +0800
Message-ID: <CADBw62r_tkGEr9kHpojAi+fJ+qUqbsc-DQgG1TUAwOdbDXTgNQ@mail.gmail.com>
Subject: Re: [PATCH 4/5] mfd: sprd-sc27xx-spi: Fix divide by zero when
 allocating register offset/mask
To:     Lee Jones <lee.jones@linaro.org>
Cc:     Johan Hovold <johan@kernel.org>, Orson Zhai <orsonzhai@gmail.com>,
        LKML <linux-kernel@vger.kernel.org>,
        linux-arm-kernel@lists.infradead.org,
        Chunyan Zhang <zhang.lyra@gmail.com>
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On Mon, Jun 29, 2020 at 10:01 PM Lee Jones <lee.jones@linaro.org> wrote:
>
> On Mon, 29 Jun 2020, Johan Hovold wrote:
>
> > On Mon, Jun 29, 2020 at 01:32:14PM +0100, Lee Jones wrote:
> > > Since ddata->irqs[] is already zeroed when allocated by devm_kcalloc() and
> > > dividing 0 by anything is still 0, there is no need to re-assign
> > > ddata->irqs[i].* values.  Instead, it should be safe to begin at 1.
> > >
> > > This fixes the following W=1 warning:
> > >
> > >  drivers/mfd/sprd-sc27xx-spi.c:255 sprd_pmic_probe() debug: sval_binop_unsigned: divide by zero
> > >
> > > Cc: Orson Zhai <orsonzhai@gmail.com>
> > > Cc: Baolin Wang <baolin.wang7@gmail.com>
> > > Cc: Chunyan Zhang <zhang.lyra@gmail.com>
> > > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > > ---
> > >  drivers/mfd/sprd-sc27xx-spi.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/mfd/sprd-sc27xx-spi.c b/drivers/mfd/sprd-sc27xx-spi.c
> > > index c305e941e435c..694a7d429ccff 100644
> > > --- a/drivers/mfd/sprd-sc27xx-spi.c
> > > +++ b/drivers/mfd/sprd-sc27xx-spi.c
> > > @@ -251,7 +251,7 @@ static int sprd_pmic_probe(struct spi_device *spi)
> > >             return -ENOMEM;
> > >
> > >     ddata->irq_chip.irqs = ddata->irqs;
> > > -   for (i = 0; i < pdata->num_irqs; i++) {
> > > +   for (i = 1; i < pdata->num_irqs; i++) {
> > >             ddata->irqs[i].reg_offset = i / pdata->num_irqs;
> > >             ddata->irqs[i].mask = BIT(i % pdata->num_irqs);
> > >     }
> >
> > This doesn't look right either.
> >
> > First, the loop is never executed if num_irqs is zero.
>
> The point of the patch is that 0 entries are never processed.
>
> However, what I appear to have overlooked is that BIT(0 % x) is not 0,
> it's 1.

Yes.

>
> > Second, the current code looks bogus too as reg_offset is always set to
> > zero and mask to BIT(i)...

Now the result is correct, since all PMIC irq mask bits are in one
register now, which means the reg_offset is always 0 can work well.
But I think the logics still can be improved if our PMIC irq numbers
are larger than 32 in future.

>
> Heh.  I wonder if/how this was tested.
>
> I'm going to wait to hear from the authors before attempting to fix
> this again.
>
> Baolin, Could you please clarify this for us please?

Yes, see above comments.

-- 
Baolin Wang