Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp3019429ybt; Mon, 29 Jun 2020 13:04:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwEkZhUnSDl9JLTB+v2q2S38UYe6GRJDymBPb4phTEwCct3ZMXIctS0Vhm4qgustfp8DGB+ X-Received: by 2002:a50:e801:: with SMTP id e1mr18898653edn.251.1593461069836; Mon, 29 Jun 2020 13:04:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593461069; cv=none; d=google.com; s=arc-20160816; b=Mk0fWOOeT11ozF32zGhhGG3o5a6Bfh4NDN4b7EQHeR7Y7aOyqWB38ogkIJ+Z9oks6A ZkTiFTn6FDSnnMH9nj2+1S4RHPB2fHI1rBo8QvgV0RG79ZC6gmw95u08RboFcO0VV2+y Y8T1/Ks4Gdbal0F5t+HSjqogEHJjQ7UtMDqJmnjWd/tP9y4R0bfBGdrP3OpuAC4hBudh w7d0T9yJVE8nKUwGJN87NfUliU6pA5f7iEkhyXAIyzNkU0HtSFa8BKyVP+FXMhyrVWba o6sTaYNH7LMVR24nEakjXfTCdzbvqDJZjPXYWFf4PVKqa+njpTRziaISLaWMAm0rl3Kr zS0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=NInZDyVx5UB1RMVTucuBshEyyDAIjGZU35YbRUa8iu8=; b=YbQoy1T8vDTP2h7+tEzwem0MqyB0sNsj0SX2Xdmzv4xO/UQRjRHF3GZJ4yPxAPw2Wb 0wbyyn0p8roVE1R2k+kjPv9aZ4O+HLgLRQQzy/6VDg8MQ96LEFxpr9KzGvbhymN8R0GK 9eZQF1wGUhntxB5MZqX37uHhZ9au9JDjg6DlvzjlOr23OMK4k+U/VW7w9u+yHoGgERXM vMcIXYnxAZcF3j3g6/7pOjKr5lVdsNr9xlbIxlJh6Y4uV7aOwROdRc9SSjJNjcYlZtPH vZcBr+i8xzD38wFDwQoqFEn40GJQQBDQHL/urhYA6jb3oR1bPXO70x9AL4Wmi6OEhrc9 0PdQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id l4si332795edi.316.2020.06.29.13.04.06; Mon, 29 Jun 2020 13:04:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387552AbgF2UCA (ORCPT + 99 others); Mon, 29 Jun 2020 16:02:00 -0400 Received: from muru.com ([72.249.23.125]:59972 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731818AbgF2TkL (ORCPT ); Mon, 29 Jun 2020 15:40:11 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id EA96381A8; Mon, 29 Jun 2020 17:13:52 +0000 (UTC) Date: Mon, 29 Jun 2020 10:12:57 -0700 From: Tony Lindgren To: Drew Fustini Cc: Rob Herring , =?utf-8?Q?Beno=C3=AEt?= Cousson , Linux-OMAP , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jason Kridner , Robert Nelson , "Mark A. Yoder" Subject: Re: [PATCH V2] ARM: dts: am33xx-l4: add gpio-ranges Message-ID: <20200629171257.GU37466@atomide.com> References: <20200610110258.GA3024740@x1> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200610110258.GA3024740@x1> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Drew Fustini [200610 04:03]: > Add gpio-ranges properties to the gpio controller nodes. > > These gpio-ranges were created based on "Table 9-10. CONTROL_MODULE > REGISTERS" in the "AM335x Technical Reference Manual" [0] and "Table > 4-2. Pin Attributes" in the "AM335x Sitara Processor datasheet" [1]. > A csv file with this data is available for reference [2]. > > These mappings are valid for all SoC's that are using am33xx-l4.dtsi. > In addition, the only TI AM33xx parts that actually exist are [0]: > AM3351, AM3352, AM3354, AM3356, AM3357, AM3358, AM3359 > > These gpio-ranges properties should be added as they describe the > relationship between a gpio line and pin control register that exists > in the hardware. For example, GPMC_A0 pin has mode 7 which is labeled > gpio1_16. conf_gpmc_a0 register is at offset 840h which makes it pin 16. > > [0] https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf > [1] http://www.ti.com/lit/ds/symlink/am3358.pdf > [2] https://gist.github.com/pdp7/6ffaddc8867973c1c3e8612cfaf72020 > [3] http://www.ti.com/processors/sitara-arm/am335x-cortex-a8/overview.html > > Signed-off-by: Drew Fustini > --- > V2 changes: > - clarify that these gpio-ranges are valid for all SoCs including that > am33xx-l4.dtsi > - describe why these gpio-ranges should be added Thanks applying into omap-for-v5.9/dt. Regards, Tony