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From:   Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To:     jbrunet@baylibre.com, linux-amlogic@lists.infradead.org
Cc:     narmstrong@baylibre.com, linux-clk@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH 0/2] clk: meson8b: add two missing gate clocks
Date:   Mon, 29 Jun 2020 22:39:02 +0200
Message-Id: <20200629203904.2989007-1-martin.blumenstingl@googlemail.com>
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While trying to figure out how to set up the video clocks on the 32-bit
SoCs I found that the current clock tree is missing two gates. This adds
the missing gates based on evidence found in the public S805 datasheet,
the GXBB clock driver and 3.10 vendor kernel.

I didn't add any Fixes tag because this clock tree is still read-only
and the HDMI PLL (the top-most clock in this tree) needs more work as
well.


Martin Blumenstingl (2):
  clk: meson: meson8b: add the vclk_en gate clock
  clk: meson: meson8b: add the vclk2_en gate clock

 drivers/clk/meson/meson8b.c | 60 ++++++++++++++++++++++++++++++-------
 drivers/clk/meson/meson8b.h |  4 ++-
 2 files changed, 53 insertions(+), 11 deletions(-)

-- 
2.27.0