Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
MIME-Version: 1.0
References: <20200630032014.22956-1-andy.tang@nxp.com> <CAHLCerO3B4Z67KP8VaF957Jkid21gLvzhS49gNeqUC+6muPkjA@mail.gmail.com>
 <DBBPR04MB609085CD69E4CCBDD49CCF66F36F0@DBBPR04MB6090.eurprd04.prod.outlook.com>
In-Reply-To: <DBBPR04MB609085CD69E4CCBDD49CCF66F36F0@DBBPR04MB6090.eurprd04.prod.outlook.com>
From:   Amit Kucheria <amit.kucheria@linaro.org>
Date:   Tue, 30 Jun 2020 11:06:56 +0530
Message-ID: <CAP245DV-_+5Ht=yP9Mnzb2vUqXDJSEeBPfbNh48mEt62PmBeWA@mail.gmail.com>
Subject: Re: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal zone support
To:     Andy Tang <andy.tang@nxp.com>
Cc:     Shawn Guo <shawnguo@kernel.org>, Leo Li <leoyang.li@nxp.com>,
        Rob Herring <robh+dt@kernel.org>,
        lakml <linux-arm-kernel@lists.infradead.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Tue, Jun 30, 2020 at 10:58 AM Andy Tang <andy.tang@nxp.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Amit Kucheria <amit.kucheria@linaro.org>
> > Sent: 2020=E5=B9=B46=E6=9C=8830=E6=97=A5 13:12
> > To: Andy Tang <andy.tang@nxp.com>
> > Cc: Shawn Guo <shawnguo@kernel.org>; Leo Li <leoyang.li@nxp.com>; Rob
> > Herring <robh+dt@kernel.org>; lakml <linux-arm-kernel@lists.infradead.o=
rg>;
> > open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> > <devicetree@vger.kernel.org>; LKML <linux-kernel@vger.kernel.org>
> > Subject: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal zo=
ne
> > support
> >
> > Caution: EXT Email
> >
> > On Tue, Jun 30, 2020 at 8:56 AM <andy.tang@nxp.com> wrote:
> > >
> > > From: Yuantian Tang <andy.tang@nxp.com>
> > >
> > > There are 2 thermal zones in ls1088a soc. Add the other thermal zone
> > > node to enable it.
> > > Also update the values in calibration table to make the temperatures
> > > monitored more precise.
> > >
> > > Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
> > > ---
> > >  .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 100
> > > +++++++++++-------
> > >  1 file changed, 62 insertions(+), 38 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > index 36a799554620..ccbbc23e6c85 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > @@ -129,19 +129,19 @@
> > >         };
> > >
> > >         thermal-zones {
> > > -               cpu_thermal: cpu-thermal {
> > > +               core-cluster {
> > >                         polling-delay-passive =3D <1000>;
> > >                         polling-delay =3D <5000>;
> > >                         thermal-sensors =3D <&tmu 0>;
> > >
> > >                         trips {
> > > -                               cpu_alert: cpu-alert {
> > > +                               core_cluster_alert:
> > core-cluster-alert
> > > + {
> > >                                         temperature =3D <85000>;
> > >                                         hysteresis =3D <2000>;
> > >                                         type =3D "passive";
> > >                                 };
> > >
> > > -                               cpu_crit: cpu-crit {
> > > +                               core_cluster_crit: core-cluster-crit =
{
> > >                                         temperature =3D <95000>;
> > >                                         hysteresis =3D <2000>;
> > >                                         type =3D "critical"; @@
> > -150,7
> > > +150,7 @@
> > >
> > >                         cooling-maps {
> > >                                 map0 {
> > > -                                       trip =3D <&cpu_alert>;
> > > +                                       trip =3D
> > <&core_cluster_alert>;
> > >                                         cooling-device =3D
> > >                                                 <&cpu0
> > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > >                                                 <&cpu1
> > > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -163,6 +163,26 @@
> > >                                 };
> > >                         };
> > >                 };
> > > +
> > > +               soc {
> > > +                       polling-delay-passive =3D <1000>;
> > > +                       polling-delay =3D <5000>;
> > > +                       thermal-sensors =3D <&tmu 1>;
> > > +
> > > +                       trips {
> > > +                               soc-alert {
> > > +                                       temperature =3D <85000>;
> > > +                                       hysteresis =3D <2000>;
> > > +                                       type =3D "passive";
> > > +                               };
> > > +
> > > +                               soc-crit {
> > > +                                       temperature =3D <95000>;
> > > +                                       hysteresis =3D <2000>;
> > > +                                       type =3D "critical";
> > > +                               };
> > > +                       };
> > > +               };
> >
> > You should also add a cooling-maps section for this thermal zone given =
that it
> > has a passive trip type. Otherwise there is no use for a passive trip t=
ype.
> It is better to have a cooling device. But there is only one cooling devi=
ce on this platform
> which is used by core-cluster. So there is no extra cooling device for it=
.
> This zone can take action when critical temp is reached. So it is still u=
seful.
> What do you suggest?

If the action taken by the core-cluster cooling-maps is the only one
that can be taken, I suggest getting rid of the the soc-alert passive
trip completely. It is not of any use.

If there is a chance that your soc thermal-zone can heat up before
your cpu-cluster zone (unlikely), you could use the same cooling
device (cpu0, cpu1) for soc thermal zone too.