Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp153049ybt; Tue, 30 Jun 2020 17:02:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJye3yLOta9IqZ/iP0z3vTtZy0CDB3vRkXhMHMMv6O9Jf/kPooZyXSx0kmr1YCerpNuQ14nX X-Received: by 2002:a17:906:c35a:: with SMTP id ci26mr5219859ejb.451.1593561763887; Tue, 30 Jun 2020 17:02:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593561763; cv=none; d=google.com; s=arc-20160816; b=rUdy07sjCeo9YO1DsjR8iWkfSxPG044RzjVOhtSocGi7swyDFdcejpbjX7PQjGvMCL GIzQWx+YRfh5s1hEE70XlR0H6an6moCtyWtQUy0bmrbgPiS5KUeTl2m1q3KJqXjqCo9X ASuzdln5zDryU44XFxj/eusdkY/0jH5cBDz5GKP+xA0vsxyjHMST7ny60TPiynyCgBX+ D3AxKfmr8Wce1O8+ibTB8oJ+nBbBKhu8RjwHXs7q2VL1AIXqNFKRxvfnP6LkMsQGacQS LbBFIiXqvmJoqlHUvq51RKk5x+Ng610BxC32st0yqDixTUKiPboFiy2lP/x6w0uoGJra iqeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=wmP8aEJrSuDbPANLVhp+EMx58hwLpDh00JZdQDiNzyI=; b=QMC7HgedFU8/6e4V5NozgWKyn6AEBa5BNR+uul6Z/7z2k1Ue+xxhZtSYNY2mR2hs6f AgVDCGEZHCYgWTN6o/vhVGZ2xhTUszyT/0d7S8QSSDeOMKSsDHCOa/SdC3ErBP4qXEuO bOAkO/7HwsQ1HJUyoVwsh0liwBksiuZXNnLTMw92Qyqo4QuW9m/BkbENtZwdUxbtuxPN rOu2zySDQqkl10fzJE7493clRUXYo72aQUF3/4Syzm1JvBrytc00kIlLUQh05swJjowD dP7kOMnXIbKmlC1wKLVEgbcmISuWUZ88kNPvKTzkoJY90MOPf1qJi9ijEOQamXGgb3JL r2og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=PP456qCv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d21si2779952ejt.197.2020.06.30.17.02.14; Tue, 30 Jun 2020 17:02:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=PP456qCv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726703AbgF3X7S (ORCPT + 99 others); Tue, 30 Jun 2020 19:59:18 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:17079 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726352AbgF3X7R (ORCPT ); Tue, 30 Jun 2020 19:59:17 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 30 Jun 2020 16:59:03 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 30 Jun 2020 16:59:16 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 30 Jun 2020 16:59:16 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 30 Jun 2020 23:59:11 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 30 Jun 2020 23:59:11 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 30 Jun 2020 16:59:11 -0700 From: Krishna Reddy To: , , , , , CC: , , , , , , , , , , , , , , Krishna Reddy Subject: [PATCH v9 1/4] iommu/arm-smmu: move TLB timeout and spin count macros Date: Tue, 30 Jun 2020 16:57:49 -0700 Message-ID: <20200630235752.8737-2-vdumpa@nvidia.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200630235752.8737-1-vdumpa@nvidia.com> References: <20200630235752.8737-1-vdumpa@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1593561543; bh=wmP8aEJrSuDbPANLVhp+EMx58hwLpDh00JZdQDiNzyI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=PP456qCveo+JyKZ6hK3+Igrag5/IXQnIgtjTKb971wTGHg4i7b+Z8N+hsfcncbA3L QQU28XlFpSNr0SOfYAl9csul1/ZWV5bzdC63GisqbyL4+ff0ziA4puQDO6H2wcPPHY EQnTtiMYb1QTPiZ5Ll8Xjq3ZNBbVwvZiL429HxCWqUyoGwFdrhJbCaV3pY4+i2vfKA U8HtsOZsidlipphE0USUs/fzPUKdUqSq97rsjaQZ3hHNi9h5FJrqKBYvm9W+QgAuTR AcxdJRiQ0FZZif+XjlxwiBI+l2mAbqt9vNGrvovMR25cQEAn2eXj9DAW1XbeQlA5tw nX6HuRM+znKxA== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move TLB timeout and spin count macros to header file to allow using the same values from vendor specific implementations. Signed-off-by: Krishna Reddy --- drivers/iommu/arm-smmu.c | 3 --- drivers/iommu/arm-smmu.h | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 243bc4cb2705b..d2054178df357 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -52,9 +52,6 @@ */ #define QCOM_DUMMY_VAL -1 =20 -#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ -#define TLB_SPIN_COUNT 10 - #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 =20 diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index d172c024be618..c7d0122a7c6ca 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -236,6 +236,8 @@ enum arm_smmu_cbar_type { /* Maximum number of context banks per SMMU */ #define ARM_SMMU_MAX_CBS 128 =20 +#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ +#define TLB_SPIN_COUNT 10 =20 /* Shared driver definitions */ enum arm_smmu_arch_version { --=20 2.26.2