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From:   Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To:     devicetree@vger.kernel.org
Cc:     Kishon Vijay Abraham I <kishon@ti.com>,
        Vinod Koul <vkoul@kernel.org>,
        Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>,
        linux-kernel@vger.kernel.org, Rob Herring <robh@kernel.org>
Subject: [PATCH] dt-bindings: phy: zynqmp-psgtr: Fix example's numbers of cells in reg
Date:   Wed,  1 Jul 2020 16:48:53 +0300
Message-Id: <20200701134853.30656-1-laurent.pinchart@ideasonboard.com>
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The DT examples are by default compiled in a parent that has
 #address-cells and #size-cells both set to 1. Fix the example
accordingly, even if it doesn't match the actual hardware, as this is
the recommended practice for DT bindings examples.

Fixes: cea0f76a483d ("dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY")
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
index 09e3cde7ebca..04d5654efb38 100644
--- a/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
+++ b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
@@ -94,8 +94,8 @@ examples:
   - |
     phy: phy@fd400000 {
         compatible = "xlnx,zynqmp-psgtr-v1.1";
-        reg = <0x0 0xfd400000 0x0 0x40000>,
-              <0x0 0xfd3d0000 0x0 0x1000>;
+        reg = <0xfd400000 0x40000>,
+              <0xfd3d0000 0x1000>;
         reg-names = "serdes", "siou";
         clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
         clock-names = "ref1", "ref2", "ref3";
-- 
Regards,

Laurent Pinchart