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Thu, 2 Jul 2020 14:19:33 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas1p1.samsung.com (KnoxPortal) with ESMTPA id 20200702051933epcas1p111c52c4ed9fa37e9a1648335dba5e479~d19m_21WD0520905209epcas1p1E; Thu, 2 Jul 2020 05:19:33 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20200702051933epsmtrp2102f67d785e96f30fcb2bae48e5ab982~d19m957ZE1271712717epsmtrp2e; Thu, 2 Jul 2020 05:19:33 +0000 (GMT) X-AuditID: b6c32a39-e6f5da8000006fa2-9c-5efd6e65d48b Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id B7.BE.08382.56E6DFE5; Thu, 2 Jul 2020 14:19:33 +0900 (KST) Received: from [10.113.221.102] (unknown [10.113.221.102]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20200702051932epsmtip25824646da779bcc1c979a726e713af94~d19mmeBft2184521845epsmtip2f; Thu, 2 Jul 2020 05:19:32 +0000 (GMT) Subject: Re: [PATCH v4 12/37] PM / devfreq: tegra20: Use MC timings for building OPP table To: Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Mikko Perttunen Cc: =?UTF-8?B?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org From: Chanwoo Choi Organization: Samsung Electronics Message-ID: <2069fb51-f043-795d-7768-0024fc9a9f4e@samsung.com> Date: Thu, 2 Jul 2020 14:30:48 +0900 User-Agent: Mozilla/5.0 (X11; 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charset="utf-8" X-Sendblock-Type: SVC_REQ_APPROVE CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20200609131458epcas1p2c774a0302bcef2c02790c2cb8cad57a0 References: <20200609131404.17523-1-digetx@gmail.com> <20200609131404.17523-13-digetx@gmail.com> <4ea7fe00-7676-3186-8222-6e0d0eb8ed1f@samsung.com> <4b22d3ee-f303-d81d-e261-187d4a46e749@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/2/20 2:07 PM, Dmitry Osipenko wrote: > 02.07.2020 07:18, Chanwoo Choi пишет: >> Hi Dmitry, >> >> On 6/9/20 10:13 PM, Dmitry Osipenko wrote: >>> The clk_round_rate() won't be usable for building OPP table once >>> interconnect support will be added to the EMC driver because that CLK API >>> function limits the rounded rate based on the clk rate that is imposed by >>> active clk-users, and thus, the rounding won't work as expected if >>> interconnect will set the minimum EMC clock rate before devfreq driver is >>> loaded. The struct tegra_mc contains memory timings which could be used by >>> the devfreq driver for building up OPP table instead of rounding clock >>> rate, this patch implements this idea. >>> >>> Signed-off-by: Dmitry Osipenko >>> --- >>> drivers/devfreq/tegra20-devfreq.c | 18 +++++++++++------- >>> 1 file changed, 11 insertions(+), 7 deletions(-) >>> >>> diff --git a/drivers/devfreq/tegra20-devfreq.c b/drivers/devfreq/tegra20-devfreq.c >>> index 6469dc69c5e0..bf504ca4dea2 100644 >>> --- a/drivers/devfreq/tegra20-devfreq.c >>> +++ b/drivers/devfreq/tegra20-devfreq.c >>> @@ -123,8 +123,7 @@ static int tegra_devfreq_probe(struct platform_device *pdev) >>> { >>> struct tegra_devfreq *tegra; >>> struct tegra_mc *mc; >>> - unsigned long max_rate; >>> - unsigned long rate; >>> + unsigned int i; >>> int err; >>> >>> mc = tegra_get_memory_controller(); >>> @@ -151,12 +150,17 @@ static int tegra_devfreq_probe(struct platform_device *pdev) >>> >>> tegra->regs = mc->regs; >>> >>> - max_rate = clk_round_rate(tegra->emc_clock, ULONG_MAX); >>> - >>> - for (rate = 0; rate <= max_rate; rate++) { >>> - rate = clk_round_rate(tegra->emc_clock, rate); >>> + if (!mc->num_timings) { >> >> Could you explain what is meaning of 'num_timing? > > The num_timings is the number of memory timings defined in a > device-tree. One timing configuration per memory clock rate. OK. I understand. > >> Also, why add the opp entry in case of mc->num_timings is zero? > > Timings may be not defined in some device-trees at all and in this case > memory always running on a fixed clock rate. You mean that 'timings' information is optional? > > The devfreq driver won't be practically useful if mc->num_timings is > zero since memory frequency can't be changed, but anyways we'd want to > load the devfreq driver in order to prevent confusion about why it's not > loaded. > > For example, you may ask somebody to show contents of > /sys/class/devfreq/tegra20-devfreq/trans_stat and the person says to you > that this file doesn't exist, now you'll have to figure out what > happened to the devfreq driver. I understand why add OPP entry point when timing is not defined on DT. But, actually, I think that you better to change 'timings' info is mandatory instead of optional. Because the devfreq driver is for DVFS and the driver supporting DVFS have to have the frequency information like OPP. Or, If you want to keep 'timing' is optional on DT, I recommend that you add one timing data to tegra mc driver when DT doesn't include the any timing information I think that is it more clear. -- Best Regards, Chanwoo Choi Samsung Electronics