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From:   Fabio Estevam <festevam@gmail.com>
Date:   Thu, 2 Jul 2020 19:29:29 -0300
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Subject: Re: [PATCH v5 3/3] ARM: imx6plus: optionally enable internal routing
 of clk_enet_ref
To:     Sven Van Asbroeck <thesven73@gmail.com>
Cc:     Shawn Guo <shawnguo@kernel.org>, Fugang Duan <fugang.duan@nxp.com>,
        Rob Herring <robh+dt@kernel.org>,
        "David S. Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        netdev <netdev@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        NXP Linux Team <linux-imx@nxp.com>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        linux-kernel <linux-kernel@vger.kernel.org>
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Hi Sven,

On Thu, Jul 2, 2020 at 2:53 PM Sven Van Asbroeck <thesven73@gmail.com> wrote:

> +       /*
> +        * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to
> +        * be the PTP clock source, instead of having to be routed through
> +        * pads.
> +        */
> +       if (of_machine_is_compatible("fsl,imx6qp")) {
> +               clksel = of_property_read_bool(np, "fsl,ptpclk-bypass-pad") ?
> +                               IMX6Q_GPR5_ENET_TXCLK_SEL_PLL :
> +                               IMX6Q_GPR5_ENET_TXCLK_SEL_PAD;
> +               regmap_update_bits(gpr, IOMUXC_GPR5,
> +                                  IMX6Q_GPR5_ENET_TXCLK_SEL_MASK, clksel);
> +       }

With the device tree approach, I think that a better place to touch
GPR5 would be inside the fec driver.

You can refer to drivers/pci/controller/dwc/pci-imx6.c and follow the
same approach for accessing the GPR register:
...
/* Grab GPR config register range */
imx6_pcie->iomuxc_gpr =
syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr")

For the property name, what about fsl,txclk-from-pll?