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Fri, 3 Jul 2020 03:53:14 +0000 From: "Liu, Yi L" To: Alex Williamson CC: "eric.auger@redhat.com" , "baolu.lu@linux.intel.com" , "joro@8bytes.org" , "Tian, Kevin" , "jacob.jun.pan@linux.intel.com" , "Raj, Ashok" , "Tian, Jun J" , "Sun, Yi Y" , "jean-philippe@linaro.org" , "peterx@redhat.com" , "Wu, Hao" , "iommu@lists.linux-foundation.org" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v3 02/14] iommu: Report domain nesting info Thread-Topic: [PATCH v3 02/14] iommu: Report domain nesting info Thread-Index: AQHWSgRQVmc9Qp+Xi0mQEumzIJrE0qj0n78AgAClxmA= Date: Fri, 3 Jul 2020 03:53:14 +0000 Message-ID: References: <1592988927-48009-1-git-send-email-yi.l.liu@intel.com> <1592988927-48009-3-git-send-email-yi.l.liu@intel.com> <20200702115454.058bd198@x1.home> In-Reply-To: <20200702115454.058bd198@x1.home> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.2.0.6 dlp-product: dlpe-windows authentication-results: redhat.com; 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x-ms-exchange-antispam-messagedata: oHLQuncbA04bo7wQW/ET5fJ4wsDOWjWPu6MKGnCZ3NwzsnkwjBYrkB08YYr/G7Gv7zylokVbS6ld7XUH26KV4TzeekZf3H42C+p1mHgkA8gcTq2t7nOahiKf15g0l0QXUPBfsQoUudGgoBxXbwicgbJ6d813lLnETNxFnIbsj2DhGNJV6wwaNvchvUiJUbljBX7j4KsEFC8O97m2B8Rwt83amxABXME0FVm2MHt5nfESaUApLvEc5k5I1wSvO8UZiouA+VBDDpRSeSJV6tFHw74pdOVOzGn7Q+3DJKTzCY19diM+EUjDKZiVvUjq7Ck64cE+WqcGPgSodCsjWOwkKv7Z3yR1kUxBaHDCcGWzceZ1BLFI1K/PT7hmvXXGD77nvPsUtNOdJlrHv5ZI8pWQfo23tkJrwBRUkpAlvFBVZr8BoYvOsGH7Zpu5zhvUxZW84Y5YGcBUHxj2wahuwRxnMYNqd4V7hkof/EDw0LmJQpOQK+XdQd95mBQCra940JH4 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM5PR11MB1435.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d152ba31-51d2-4546-015c-08d81f049cf8 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jul 2020 03:53:14.5145 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: T+/sL+heOP52hMKzlkD0DCyrTbwSmEMWz7wforblpbfDx1Fsfl3fftatEPA7xJi+SvvU7NXxboPC78pHSOO6aQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB2537 X-OriginatorOrg: intel.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Alex Williamson > Sent: Friday, July 3, 2020 1:55 AM >=20 > On Wed, 24 Jun 2020 01:55:15 -0700 > Liu Yi L wrote: >=20 > > IOMMUs that support nesting translation needs report the capability > > info to userspace, e.g. the format of first level/stage paging structur= es. > > > > This patch reports nesting info by DOMAIN_ATTR_NESTING. Caller can get > > nesting info after setting DOMAIN_ATTR_NESTING. > > > > v2 -> v3: > > *) remvoe cap/ecap_mask in iommu_nesting_info. > > *) reuse DOMAIN_ATTR_NESTING to get nesting info. > > *) return an empty iommu_nesting_info for SMMU drivers per Jean' > > suggestion. > > > > Cc: Kevin Tian > > CC: Jacob Pan > > Cc: Alex Williamson > > Cc: Eric Auger > > Cc: Jean-Philippe Brucker > > Cc: Joerg Roedel > > Cc: Lu Baolu > > Signed-off-by: Liu Yi L > > Signed-off-by: Jacob Pan > > --- > > drivers/iommu/arm-smmu-v3.c | 29 ++++++++++++++++++++-- > > drivers/iommu/arm-smmu.c | 29 ++++++++++++++++++++-- > > include/uapi/linux/iommu.h | 59 > > +++++++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 113 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c > > index f578677..0c45d4d 100644 > > --- a/drivers/iommu/arm-smmu-v3.c > > +++ b/drivers/iommu/arm-smmu-v3.c > > @@ -3019,6 +3019,32 @@ static struct iommu_group > *arm_smmu_device_group(struct device *dev) > > return group; > > } > > > > +static int arm_smmu_domain_nesting_info(struct arm_smmu_domain > *smmu_domain, > > + void *data) > > +{ > > + struct iommu_nesting_info *info =3D (struct iommu_nesting_info *) dat= a; > > + u32 size; > > + > > + if (!info || smmu_domain->stage !=3D ARM_SMMU_DOMAIN_NESTED) > > + return -ENODEV; > > + > > + size =3D sizeof(struct iommu_nesting_info); > > + > > + /* > > + * if provided buffer size is not equal to the size, should > > + * return 0 and also the expected buffer size to caller. > > + */ > > + if (info->size !=3D size) { > > + info->size =3D size; > > + return 0; > > + } > > + > > + /* report an empty iommu_nesting_info for now */ > > + memset(info, 0x0, size); > > + info->size =3D size; > > + return 0; > > +} > > + > > static int arm_smmu_domain_get_attr(struct iommu_domain *domain, > > enum iommu_attr attr, void *data) { @@ - > 3028,8 +3054,7 @@ > > static int arm_smmu_domain_get_attr(struct iommu_domain *domain, > > case IOMMU_DOMAIN_UNMANAGED: > > switch (attr) { > > case DOMAIN_ATTR_NESTING: > > - *(int *)data =3D (smmu_domain->stage =3D=3D > ARM_SMMU_DOMAIN_NESTED); > > - return 0; > > + return arm_smmu_domain_nesting_info(smmu_domain, > data); > > default: > > return -ENODEV; > > } > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index > > 243bc4c..908607d 100644 > > --- a/drivers/iommu/arm-smmu.c > > +++ b/drivers/iommu/arm-smmu.c > > @@ -1506,6 +1506,32 @@ static struct iommu_group > *arm_smmu_device_group(struct device *dev) > > return group; > > } > > > > +static int arm_smmu_domain_nesting_info(struct arm_smmu_domain > *smmu_domain, > > + void *data) > > +{ > > + struct iommu_nesting_info *info =3D (struct iommu_nesting_info *) dat= a; > > + u32 size; > > + > > + if (!info || smmu_domain->stage !=3D ARM_SMMU_DOMAIN_NESTED) > > + return -ENODEV; > > + > > + size =3D sizeof(struct iommu_nesting_info); > > + > > + /* > > + * if provided buffer size is not equal to the size, should > > + * return 0 and also the expected buffer size to caller. > > + */ > > + if (info->size !=3D size) { > > + info->size =3D size; > > + return 0; > > + } > > + > > + /* report an empty iommu_nesting_info for now */ > > + memset(info, 0x0, size); > > + info->size =3D size; > > + return 0; > > +} > > + > > static int arm_smmu_domain_get_attr(struct iommu_domain *domain, > > enum iommu_attr attr, void *data) { @@ - > 1515,8 +1541,7 @@ > > static int arm_smmu_domain_get_attr(struct iommu_domain *domain, > > case IOMMU_DOMAIN_UNMANAGED: > > switch (attr) { > > case DOMAIN_ATTR_NESTING: > > - *(int *)data =3D (smmu_domain->stage =3D=3D > ARM_SMMU_DOMAIN_NESTED); > > - return 0; > > + return arm_smmu_domain_nesting_info(smmu_domain, > data); > > default: > > return -ENODEV; > > } > > diff --git a/include/uapi/linux/iommu.h b/include/uapi/linux/iommu.h > > index 1afc661..898c99a 100644 > > --- a/include/uapi/linux/iommu.h > > +++ b/include/uapi/linux/iommu.h > > @@ -332,4 +332,63 @@ struct iommu_gpasid_bind_data { > > } vendor; > > }; > > > > +/* > > + * struct iommu_nesting_info - Information for nesting-capable IOMMU. > > + * user space should check it before using > > + * nesting capability. > > + * > > + * @size: size of the whole structure > > + * @format: PASID table entry format, the same definition with > > + * @format of struct iommu_gpasid_bind_data. > > + * @features: supported nesting features. > > + * @flags: currently reserved for future extension. > > + * @data: vendor specific cap info. > > + * > > + * +---------------+--------------------------------------------------= --+ > > + * | feature | Notes = | > > + * > > > ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D > > ++ > > + * | SYSWIDE_PASID | Kernel manages PASID in system wide, PASIDs used= | > > + * | | in the system should be allocated by host kernel= | > > + * +---------------+--------------------------------------------------= --+ > > + * | BIND_PGTBL | bind page tables to host PASID, the PASID could = | > > + * | | either be a host PASID passed in bind request or= | > > + * | | default PASIDs (e.g. default PASID of aux-domain= ) | > > + * +---------------+--------------------------------------------------= --+ > > + * | CACHE_INVLD | mandatory feature for nesting capable IOMMU = | > > + * > > ++---------------+---------------------------------------------------- > > ++ >=20 > Agree with the previous comments on these descriptions and Kevin's sugges= tions. I see. will follow the suggestions. > > + * > > + */ > > +struct iommu_nesting_info { > > + __u32 size; > > + __u32 format; > > + __u32 features; > > +#define IOMMU_NESTING_FEAT_SYSWIDE_PASID (1 << 0) > > +#define IOMMU_NESTING_FEAT_BIND_PGTBL (1 << 1) > > +#define IOMMU_NESTING_FEAT_CACHE_INVLD (1 << 2) > > + __u32 flags; > > + __u8 data[]; >=20 > How does the user determine which vendor structure is provided in data[]? it can be deduced by the @format field. @format field follows the definitio= n in the iommu_gpasid_bind_data. struct iommu_gpasid_bind_data { __u32 argsz; #define IOMMU_GPASID_BIND_VERSION_1 1 __u32 version; #define IOMMU_PASID_FORMAT_INTEL_VTD 1 __u32 format; #define IOMMU_SVA_GPASID_VAL (1 << 0) /* guest PASID valid */ __u64 flags; __u64 gpgd; __u64 hpasid; __u64 gpasid; __u32 addr_width; __u8 padding[12]; /* Vendor specific data */ union { struct iommu_gpasid_bind_data_vtd vtd; } vendor; }; Regards, Yi Liu > Thanks, >=20 > Alex >=20 > > +}; > > + > > +/* > > + * struct iommu_nesting_info_vtd - Intel VT-d specific nesting info > > + * > > + * > > + * @flags: VT-d specific flags. Currently reserved for future > > + * extension. > > + * @addr_width: The output addr width of first level/stage translation > > + * @pasid_bits: Maximum supported PASID bits, 0 represents no PASID > > + * support. > > + * @cap_reg: Describe basic capabilities as defined in VT-d capability > > + * register. > > + * @ecap_reg: Describe the extended capabilities as defined in VT-d > > + * extended capability register. > > + */ > > +struct iommu_nesting_info_vtd { > > + __u32 flags; > > + __u16 addr_width; > > + __u16 pasid_bits; > > + __u64 cap_reg; > > + __u64 ecap_reg; > > +}; > > + > > #endif /* _UAPI_IOMMU_H */