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[23.128.96.18]) by mx.google.com with ESMTP id e23si8202272edy.264.2020.07.03.10.08.38; Fri, 03 Jul 2020 10:09:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KwXmSjzk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726782AbgGCRFy (ORCPT + 99 others); Fri, 3 Jul 2020 13:05:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726774AbgGCRFx (ORCPT ); Fri, 3 Jul 2020 13:05:53 -0400 Received: from mail-qv1-xf43.google.com (mail-qv1-xf43.google.com [IPv6:2607:f8b0:4864:20::f43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A836AC061794 for ; Fri, 3 Jul 2020 10:05:53 -0700 (PDT) Received: by mail-qv1-xf43.google.com with SMTP id h18so14532823qvl.3 for ; Fri, 03 Jul 2020 10:05:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=uOxIRzqV33cwYiOayyd2WFVo6gUD/TXwDz0UDM2FxKs=; b=KwXmSjzk/in70DsvZW/OqlJVbh7RjTtMHjUSsmmNvyH5aE7ZNj6NcWsyaamq+b+79b VgSghhNlE0KbRfmk9RYQYiMvyqWl1/fsjdD9sIrMxJIJ007fdJxPuKPyqvtAYdQ5lMjA NYCDxzvIrgOcaa0SRN+rU+dDlfqeeWRrAGsLe6tS2ojOxffdNA0NFJb9Dkd4gpfYNGpF S1Dmd5e//uzU3TSzYsXNe+EnbbVjC9Zy2i322fansr6nSoSKGwqOYRum47dWPnJci6lN +SNCJvdrTxsGybqIIbnSrud4z1YtiSwB6SlWOqx4pg5j/eFpO+uVgGDNJnA4nRCPA5xp sruA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=uOxIRzqV33cwYiOayyd2WFVo6gUD/TXwDz0UDM2FxKs=; b=trC0sqAFCX1NSFJhdUsO9qw+yiR7v/x21HyEb31ULytuute9REqLGUHinGAysXZRbN z5NZ7poCZjGqKXmxOQADFwwLTMNvsFkIhJQzUEgV7acWwUDxsfDBfR6vaY2JSNcVPNh/ tJVBOEkd9TAmntNJOVV+PLxJXfBVtdb9z852tlyjB9VKyl1EWf60MTuYos07BWNwVIfK 0xvkZ3/C6oSbYHTEHfXuEgYoLQBQrfhevrZAykOyXtv1xk8/aFxCgdNgvQ9stwTr1nSo yTyqeXDdzBCSKVat6bcLzDHo0xip0SuCxQ2I4RIEfcuM522jdZGhaIpDGgMP0tGNc3/o ogJQ== X-Gm-Message-State: AOAM533eOmAenukiKfefahEZltukMz2BGdzCLdwnj6BuaDncXiwpthPB C9XxYflk8ap5d6uD3kpbAsq7Vt/lN/RxKBH0A8Yd8A== X-Received: by 2002:a0c:b315:: with SMTP id s21mr35952885qve.53.1593795952915; Fri, 03 Jul 2020 10:05:52 -0700 (PDT) MIME-Version: 1.0 References: <1593699479-1445-1-git-send-email-grzegorz.jaszczyk@linaro.org> <1593699479-1445-6-git-send-email-grzegorz.jaszczyk@linaro.org> In-Reply-To: From: Grzegorz Jaszczyk Date: Fri, 3 Jul 2020 19:05:41 +0200 Message-ID: Subject: Re: [PATCHv3 5/6] irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs To: Marc Zyngier Cc: tglx@linutronix.de, jason@lakedaemon.net, "Anna, Suman" , robh+dt@kernel.org, Lee Jones , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, david@lechnology.com, "Mills, William" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2 Jul 2020 at 19:59, Marc Zyngier wrote: > > On 2020-07-02 15:17, Grzegorz Jaszczyk wrote: > > From: Suman Anna > > > > The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS > > IP, > > commonly called ICSSG. The PRUSS INTC present within the ICSSG supports > > more System Events (160 vs 64), more Interrupt Channels and Host > > Interrupts > > (20 vs 10) compared to the previous generation PRUSS INTC instances. > > The > > first 2 and the last 10 of these host interrupt lines are used by the > > PRU and other auxiliary cores and sub-modules within the ICSSG, with 8 > > host interrupts connected to MPU. The host interrupts 5, 6, 7 are also > > connected to the other ICSSG instances within the SoC and can be > > partitioned as per system integration through the board dts files. > > > > Enhance the PRUSS INTC driver to add support for this ICSSG INTC > > instance. This support is added using specific compatible and match > > data and updating the code to use this data instead of the current > > hard-coded macros. The INTC config structure is updated to use the > > higher events and channels on all SoCs, while limiting the actual > > processing to only the relevant number of events/channels/interrupts. > > > > Signed-off-by: Suman Anna > > Signed-off-by: Grzegorz Jaszczyk > > --- > > v2->v3: > > - Change patch order: use it directly after "irqchip/irq-pruss-intc: > > Implement irq_{get,set}_irqchip_state ops" and before new > > "irqchip/irq-pruss-intc: Add event mapping support" in order to > > reduce > > diff. > > The diff would be even smaller if you introduced a variable number of > inputs the first place, i.e. in patch #2. Most if this patch just > retrofits it. Please squash these changes into that initial patch, > and only add the platform stuff here. Sure I will do that. Thank you, Grzegorz