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Received: from [189.59.31.158] (port=57190 helo=[192.168.15.5]) by br164.hostgator.com.br with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.93) (envelope-from ) id 1jsDKs-000TzD-D1; Sun, 05 Jul 2020 19:42:10 -0300 Subject: Re: [PATCH v1] arm64: dts: actions: Fix smp Bringing up secondary CPUs To: =?UTF-8?Q?Andreas_F=c3=a4rber?= Cc: manivannan.sadhasivam@linaro.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-actions@lists.infradead.org References: <20200705191944.404933-1-matheus@castello.eng.br> <60c25ef8-761d-9108-a8b1-ea15678c496c@suse.de> From: Matheus Castello Message-ID: <24c87b5b-d378-bcfa-d557-0dcba5199c1b@castello.eng.br> Date: Sun, 5 Jul 2020 19:42:06 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <60c25ef8-761d-9108-a8b1-ea15678c496c@suse.de> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: pt-BR Content-Transfer-Encoding: 8bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - br164.hostgator.com.br X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - castello.eng.br X-BWhitelist: no X-Source-IP: 189.59.31.158 X-Source-L: No X-Exim-ID: 1jsDKs-000TzD-D1 X-Source: X-Source-Args: X-Source-Dir: X-Source-Sender: ([192.168.15.5]) [189.59.31.158]:57190 X-Source-Auth: matheus@castello.eng.br X-Email-Count: 7 X-Source-Cap: Y2FzdGUyNDg7Y2FzdGUyNDg7YnIxNjQuaG9zdGdhdG9yLmNvbS5icg== X-Local-Domain: yes Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andreas, Em 7/5/20 7:09 PM, Andreas Färber escreveu: > Hi Matheus, > > Am 05.07.20 um 21:19 schrieb Matheus Castello: >> Change the enable-method to fix the failed to boot errors: >> >> [    0.040330] smp: Bringing up secondary CPUs ... >> [    0.040683] psci: failed to boot CPU1 (-22) >> [    0.040691] CPU1: failed to boot: -22 >> [    0.041062] psci: failed to boot CPU2 (-22) >> [    0.041071] CPU2: failed to boot: -22 >> [    0.041408] psci: failed to boot CPU3 (-22) >> [    0.041417] CPU3: failed to boot: -22 >> [    0.041443] smp: Brought up 1 node, 1 CPU >> [    0.041451] SMP: Total of 1 processors activated. >> >> Tested on Caninos Labrador v3 based on Actions Semi S700. >> >> Signed-off-by: Matheus Castello >> --- >>   arch/arm64/boot/dts/actions/s700.dtsi | 33 +++++++++++++++++++-------- >>   1 file changed, 23 insertions(+), 10 deletions(-) > > NACK. > > For starters, if this were an actual fix, it should have a Fixes header. > > Don't do random changes in a single patch and call it a "fix". I don't > see what changing the cell size has to do with smp, nor adding L2 cache. > The latter could be a patch of its own, after fixes are applied (to > avoid conflicts when backporting that fix to older branches). A cell > size of two used to be perfectly valid, please checking the DT binding. > > Finally, you're changing generic S700 code here - you can't just break > Cubieboard7 just because your Labrador has too old BL31 firmware. Can't Sorry for that, got it. > you just update its TF-A firmware and use the standard PSCI interface > for Linux? If not, then you should add your workaround to your > module's/board's .dts(i) instead of the SoC's .dtsi. > Yes, the vendor does not seem to support this for now. I think for now the best thing to do is to leave the workaround on the module's .dtsi. Thank you for the tips. > Thanks, > Andreas > BR, Matheus Castello