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Mon, 6 Jul 2020 08:04:26 +0000 Date: Mon, 6 Jul 2020 16:04:11 +0800 From: Jisheng Zhang To: Will Deacon Cc: Robin Murphy , Mark Rutland , Catalin Marinas , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/3] arm64: perf: add support for Cortex-A55/A75/A76 Message-ID: <20200706160411.19d91904@xhacker.debian> In-Reply-To: <20200703123346.GB18953@willie-the-truck> References: <20200619184423.5e61a838@xhacker.debian> <20200703123346.GB18953@willie-the-truck> X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-pc-linux-gnu) Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-ClientProxiedBy: TYCPR01CA0002.jpnprd01.prod.outlook.com (2603:1096:405::14) To BYAPR03MB3573.namprd03.prod.outlook.com (2603:10b6:a02:ae::15) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from xhacker.debian (124.74.246.114) by TYCPR01CA0002.jpnprd01.prod.outlook.com (2603:1096:405::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3153.20 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: STHMby97wEEW3LTOL3YhfWnmK/7Ra8q3VufgZI7ztPxXocJ+QcYG+yJgCU67VQfKDvOPgt5k2ytfLpf5wHJ3y/9KEzoPa5tGEQEZx1PTcmAVJ4iDvTg1S4WenEH4tnJsfvtCQiARmUtcne6Ry2y00w82uxjEtSb0Z3C2/55rx1yD1k1Y2u+U2RSbA6/5/42q5vbYpI5e9tPXkmHn61LDuqkGmU+J+si/8rhD+G1/eYEAQmP1dREbItqNdvAY5lmDoUwErBzlKwV3shM4hMd9e28yLi4dT0TzvXvxThIcjDUWGQF9exO2Jlic1TKuah2PEOFYyY2QAkxZSkjgriEMO2hPGxsLjQ/it5jwbbX7ETDH+2UpgJ2nTCSg3mic5+PgZnTyiKVnlPAHbr8MKURhJ3tY5X7WRIhA2vBp0qV12/+4+WaRzt8tOBmAymLosp5eumdl0M+jmzcXTEFymWD43TDEL8JHpSEIJ5YUWkvLLWE99eZ+M8zO98hboZC2OGjU X-OriginatorOrg: synaptics.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4afbf8af-8255-4c75-4272-08d821833385 X-MS-Exchange-CrossTenant-AuthSource: BYAPR03MB3573.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2020 08:04:26.4857 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335d1fbc-2124-4173-9863-17e7051a2a0e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: UdlQzg2Dn9bREZiYkOOldN3xjveozEi2uYCxwvFqS8UW5mIjhJvpJxbacWq9aKRX0JdzosOSWgiYa6plOtPbYg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR03MB3749 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Will, On Fri, 3 Jul 2020 13:33:47 +0100 Will Deacon wrote: > > > On Fri, Jun 19, 2020 at 06:44:37PM +0800, Jisheng Zhang wrote: > > The Cortex-A55/A75/A76 use some implementation defined perf events. > > Add the support. > > > > Jisheng Zhang (3): > > arm64: perf: add support for Cortex-A55 > > arm64: perf: add support for Cortex-A75 > > arm64: perf: add support for Cortex-A76 > > > > arch/arm64/kernel/perf_event.c | 49 +++++++++++++++++++++++++++++++--- > > 1 file changed, 45 insertions(+), 4 deletions(-) > > Do we really need this? I'd prefer for this stuff to live in userspace IMHO, this stuff is to add a relationship between linux standard HW events and ARM PMU events, take CA55 for example: w/o the stuff, perf -e PREFETCH_LINEFILL w/ the stuff, perf -e L1-dcache-prefetch-misses But indeed, we also need to add json descriptions in perf tool, I'll submit patches. Thanks > now that the perf tool has supported JSON event descriptions for a while, > and the in-kernel driver advertises the architected events advertised > by PMCEID*. > > Will