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Set irq level low trigger to keep irq always be handled. Signed-off-by: Gene Chen --- drivers/mfd/mt6360-core.c | 25 ++++++++----------------- include/linux/mfd/mt6360.h | 6 +++--- 2 files changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c index 5dfc13e..2dd5918 100644 --- a/drivers/mfd/mt6360-core.c +++ b/drivers/mfd/mt6360-core.c @@ -208,24 +208,16 @@ static const struct regmap_irq mt6360_irqs[] = { REGMAP_IRQ_REG_LINE(MT6360_LDO7_PGB_EVT, 8), }; -static int mt6360_pmu_handle_post_irq(void *irq_drv_data) -{ - struct mt6360_data *data = irq_drv_data; - - return regmap_update_bits(data->regmap, - MT6360_PMU_IRQ_SET, MT6360_IRQ_RETRIG, MT6360_IRQ_RETRIG); -} - -static struct regmap_irq_chip mt6360_irq_chip = { +static const struct regmap_irq_chip mt6360_irq_chip = { + .name = "mt6360_irqs", .irqs = mt6360_irqs, .num_irqs = ARRAY_SIZE(mt6360_irqs), - .num_regs = MT6360_PMU_IRQ_REGNUM, - .mask_base = MT6360_PMU_CHG_MASK1, - .status_base = MT6360_PMU_CHG_IRQ1, - .ack_base = MT6360_PMU_CHG_IRQ1, + .num_regs = MT6360_IRQ_REGNUM, + .mask_base = MT6360_REG_PMU_CHGMASK1, + .status_base = MT6360_REG_PMU_CHGIRQ1, + .ack_base = MT6360_REG_PMU_CHGIRQ1, .init_ack_masked = true, .use_ack = true, - .handle_post_irq = mt6360_pmu_handle_post_irq, }; static const struct regmap_config mt6360_pmu_regmap_config = { @@ -339,10 +331,9 @@ static int mt6360_probe(struct i2c_client *client) return -ENODEV; } - mt6360_irq_chip.irq_drv_data = data; ret = devm_regmap_add_irq_chip(&client->dev, data->regmap, client->irq, - IRQF_TRIGGER_FALLING, 0, - &mt6360_irq_chip, &data->irq_data); + IRQF_ONESHOT, 0, &mt6360_irq_chip, + &data->irq_data); if (ret) { dev_err(&client->dev, "Failed to add Regmap IRQ Chip\n"); return ret; diff --git a/include/linux/mfd/mt6360.h b/include/linux/mfd/mt6360.h index 76077e4..9fc6718 100644 --- a/include/linux/mfd/mt6360.h +++ b/include/linux/mfd/mt6360.h @@ -179,7 +179,7 @@ struct mt6360_data { #define MT6360_PMU_SPARE2 (0xA0) #define MT6360_PMU_SPARE3 (0xB0) #define MT6360_PMU_SPARE4 (0xC0) -#define MT6360_PMU_CHG_IRQ1 (0xD0) +#define MT6360_REG_PMU_CHGIRQ1 (0xD0) #define MT6360_PMU_CHG_IRQ2 (0xD1) #define MT6360_PMU_CHG_IRQ3 (0xD2) #define MT6360_PMU_CHG_IRQ4 (0xD3) @@ -211,7 +211,7 @@ struct mt6360_data { #define MT6360_PMU_BUCK2_STAT (0xED) #define MT6360_PMU_LDO_STAT1 (0xEE) #define MT6360_PMU_LDO_STAT2 (0xEF) -#define MT6360_PMU_CHG_MASK1 (0xF0) +#define MT6360_REG_PMU_CHGMASK1 (0xF0) #define MT6360_PMU_CHG_MASK2 (0xF1) #define MT6360_PMU_CHG_MASK3 (0xF2) #define MT6360_PMU_CHG_MASK4 (0xF3) @@ -230,7 +230,7 @@ struct mt6360_data { #define MT6360_PMU_MAXREG (MT6360_PMU_LDO_MASK2) /* MT6360_PMU_IRQ_SET */ -#define MT6360_PMU_IRQ_REGNUM (MT6360_PMU_LDO_IRQ2 - MT6360_PMU_CHG_IRQ1 + 1) +#define MT6360_IRQ_REGNUM 16 #define MT6360_IRQ_RETRIG BIT(2) #define CHIP_VEN_MASK (0xF0) -- 2.7.4