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[209.85.217.52]) by smtp.gmail.com with ESMTPSA id p123sm89710vsd.9.2020.07.07.07.52.51 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Jul 2020 07:52:52 -0700 (PDT) Received: by mail-vs1-f52.google.com with SMTP id p25so14865935vsg.4 for ; Tue, 07 Jul 2020 07:52:51 -0700 (PDT) X-Received: by 2002:a67:31cc:: with SMTP id x195mr41265042vsx.101.1594133571467; Tue, 07 Jul 2020 07:52:51 -0700 (PDT) MIME-Version: 1.0 References: <20200622144929.230498-1-dianders@chromium.org> <20200622074845.v4.3.I68222d0b5966f652f29dd3a73ab33551a6e3b7e0@changeid> In-Reply-To: <20200622074845.v4.3.I68222d0b5966f652f29dd3a73ab33551a6e3b7e0@changeid> From: Doug Anderson Date: Tue, 7 Jul 2020 07:52:38 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 3/4] nvmem: qfprom: Add fuse blowing support To: Srinivas Kandagatla , Rob Herring , Bjorn Andersson , Andy Gross Cc: mturney@codeaurora.org, Jeffrey Hugo , Rajendra Nayak , dhavalp@codeaurora.org, Sai Prakash Ranjan , sparate@codeaurora.org, linux-arm-msm , mkurumel@codeaurora.org, Ravi Kumar Bokka , LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Mon, Jun 22, 2020 at 7:49 AM Douglas Anderson wrote: > > From: Ravi Kumar Bokka > > This patch adds support for blowing fuses to the qfprom driver if the > required properties are defined in the device tree. > > Signed-off-by: Ravi Kumar Bokka > Signed-off-by: Douglas Anderson > --- > > Changes in v4: > - Only get clock/regulator if all address ranges are provided. > - Don't use optional version of clk_get now. > - Clock name is "core", not "sec". > - Cleaned up error message if couldn't get clock. > - Fixed up minor version mask. > - Use GENMASK to generate masks. > > Changes in v3: > - Don't provide "reset" value for things; just save/restore. > - Use the major/minor version read from 0x6000. > - Reading should still read "corrected", not "raw". > - Added a sysfs knob to allow you to read "raw" instead of "corrected" > - Simplified the SoC data structure. > - No need for quite so many levels of abstraction for clocks/regulator. > - Don't set regulator voltage. Rely on device tree to make sure it's right. > - Properly undo things in the case of failure. > - Don't just keep enabling the regulator over and over again. > - Enable / disable the clock each time > - Polling every 100 us but timing out in 10 us didn't make sense; swap. > - No reason for 100 us to be SoC specific. > - No need for reg-names. > - We shouldn't be creating two separate nvmem devices. > > drivers/nvmem/qfprom.c | 314 +++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 303 insertions(+), 11 deletions(-) > > diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c > index 8a91717600be..0a8576f2d4c6 100644 > --- a/drivers/nvmem/qfprom.c > +++ b/drivers/nvmem/qfprom.c > @@ -3,57 +3,349 @@ > * Copyright (C) 2015 Srinivas Kandagatla > */ > > +#include > #include > +#include > +#include > +#include > #include > #include > -#include > #include > #include > +#include > + > +/* Blow timer clock frequency in Mhz */ > +#define QFPROM_BLOW_TIMER_OFFSET 0x03c > + > +/* Amount of time required to hold charge to blow fuse in micro-seconds */ > +#define QFPROM_FUSE_BLOW_POLL_US 10 > +#define QFPROM_FUSE_BLOW_TIMEOUT_US 100 A quick follow up found that, in some cases, a timeout of 100 us wasn't enough. Changing the above to: poll - 100 us timeout - 1000 us ...fixed the problems. I'm happy to: * Spin the whole series to change those 2 numbers. * Have those numbers changed by a maintainer when patches are applied. * Sit tight and wait for additional feedback before taking action. Given that I've resolved previous feedback, I've been assuming that the series looks fine and we're sitting waiting for Rob Herring's blessings on the bindings before landing. Is that correct? -Doug