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[23.128.96.18]) by mx.google.com with ESMTP id d2si15250703ejb.118.2020.07.07.14.49.51; Tue, 07 Jul 2020 14:50:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729214AbgGGVsj (ORCPT + 99 others); Tue, 7 Jul 2020 17:48:39 -0400 Received: from mga12.intel.com ([192.55.52.136]:55515 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728357AbgGGVsj (ORCPT ); Tue, 7 Jul 2020 17:48:39 -0400 IronPort-SDR: fBAQCPB2ml5WkV1FzOMhLnX/0jW2tnbd6qw1hTQPV7BS+lTfB3FqXXgE+MWdb9lgspfteZceGN FIZsIk6vOsSQ== X-IronPort-AV: E=McAfee;i="6000,8403,9675"; a="127297091" X-IronPort-AV: E=Sophos;i="5.75,325,1589266800"; d="scan'208";a="127297091" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2020 14:48:39 -0700 IronPort-SDR: MvfWCAMLMSvaF6Pl5E6Cy0a7vKpQKvvmYdv1ZRk7J6adXo3IqHzTbey0egARtRcQOxz14O2Gbk U5vVjOw76KmQ== X-IronPort-AV: E=Sophos;i="5.75,325,1589266800"; d="scan'208";a="457262991" Received: from unknown (HELO [10.255.2.196]) ([10.255.2.196]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2020 14:48:30 -0700 Subject: Re: [PATCH 2/4] KVM: x86: Introduce paravirt feature CR0/CR4 pinning To: Sean Christopherson Cc: "Andersen, John" , corbet@lwn.net, pbonzini@redhat.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com, shuah@kernel.org, liran.alon@oracle.com, drjones@redhat.com, rick.p.edgecombe@intel.com, kristen@linux.intel.com, vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, mchehab+huawei@kernel.org, gregkh@linuxfoundation.org, paulmck@kernel.org, pawan.kumar.gupta@linux.intel.com, jgross@suse.com, mike.kravetz@oracle.com, oneukum@suse.com, luto@kernel.org, peterz@infradead.org, fenghua.yu@intel.com, reinette.chatre@intel.com, vineela.tummalapalli@intel.com, dave.hansen@linux.intel.com, arjan@linux.intel.com, caoj.fnst@cn.fujitsu.com, bhe@redhat.com, nivedita@alum.mit.edu, keescook@chromium.org, dan.j.williams@intel.com, eric.auger@redhat.com, aaronlewis@google.com, peterx@redhat.com, makarandsonare@google.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, kernel-hardening@lists.openwall.com References: <20200617190757.27081-1-john.s.andersen@intel.com> <20200617190757.27081-3-john.s.andersen@intel.com> <0fa9682e-59d4-75f7-366f-103d6b8e71b8@intel.com> <20200618144314.GB23@258ff54ff3c0> <124a59a3-a603-701b-e3bb-61e83d70b20d@intel.com> <20200707211244.GN20096@linux.intel.com> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200707211244.GN20096@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/7/20 2:12 PM, Sean Christopherson wrote: >>>> Let's say Intel loses its marbles and adds a CR4 bit that lets userspace >>>> write to kernel memory. Linux won't set it, but an attacker would go >>>> after it, first thing. > That's an orthogonal to pinning. KVM never lets the guest set CR4 bits that > are unknown to KVM. Supporting CR4.NO_MARBLES would require an explicit KVM > change to allow it to be set by the guest, and would also require a userspace > VMM to expose NO_MARBLES to the guest. > > That being said, this series should supporting pinning as much as possible, > i.e. if the bit can be exposed to the guest and doesn't require special > handling in KVM, allow it to be pinned. E.g. TS is a special case because > pinning would require additional emulator support and IMO isn't interesting > enough to justify the extra complexity. At a glance, I don't see anything > that would prevent pinning FSGSBASE. Thanks for filling in the KVM picture. If we're supporting as much pinning as possible, can we also add something to make it inconvenient for someone to both make a CR4 bit known to KVM *and* ignore the pinning aspects? We should really make folks think about it. Something like: #define KVM_CR4_KNOWN 0xff #define KVM_CR4_PIN_ALLOWED 0xf0 #define KVM_CR4_PIN_NOT_ALLOWED 0x0f BUILD_BUG_ON(KVM_CR4_KNOWN != (KVM_CR4_PIN_ALLOWED|KVM_CR4_PIN_NOT_ALLOWED)); So someone *MUST* make an active declaration about new bits being pinned or not?