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Peter Anvin" , Kyung Min Park , Josh Poimboeuf , Greg KH , Andi Kleen , Dave Hansen , Tony Luck , "Ravi V. Shankar" , fenghua.yu@intel.com Subject: Re: [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction Message-ID: <20200708022102.GA25016@ranerica-svr.sc.intel.com> References: <1594088183-7187-1-git-send-email-cathy.zhang@intel.com> <1594088183-7187-2-git-send-email-cathy.zhang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 07, 2020 at 09:36:15AM -0700, Andy Lutomirski wrote: > On Mon, Jul 6, 2020 at 7:21 PM Cathy Zhang wrote: > > > > This instruction gives software a way to force the processor to complete > > all modifications to flags, registers and memory from previous instructions > > and drain all buffered writes to memory before the next instruction is > > fetched and executed. > > > > The same effect can be obtained using the cpuid instruction. However, > > cpuid causes modification on the eax, ebx, ecx, and ecx regiters; it > > also causes a VM exit. > > > > A processor supports SERIALIZE instruction if CPUID.0x0x.0x0:EDX[14] is > > present. The CPU feature flag is shown as "serialize" in /proc/cpuinfo. > > > > Detailed information on the instructions and CPUID feature flag SERIALIZE > > can be found in the latest Intel Architecture Instruction Set Extensions > > and Future Features Programming Reference and Intel 64 and IA-32 > > Architectures Software Developer's Manual. > > Can you also wire this up so sync_core() uses it? I am cc'ing Fenghua, who has volunteered to work on this. Addind support for SERIALIZE in sync_core() should not block merging these patches, correct? Thanks and BR, Ricardo