Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp247146ybt; Tue, 7 Jul 2020 22:04:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwG8OnfXXRSKymoleh3nTrQr/2TlfW1q1X2n+qmZAMYwCG76imS8zF7AizNd9L8sVUuUBqM X-Received: by 2002:a50:9b5d:: with SMTP id a29mr62316436edj.68.1594184645144; Tue, 07 Jul 2020 22:04:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594184645; cv=none; d=google.com; s=arc-20160816; b=z4WTWUs1QzfejZUGpDYlp3YZgqVs23GsHFMGIvnJ/SKyVqDn6H6/AovSKi11vTHDzl w34nQz33N3aZSNxDvc1imd/n+aSSbwFZkGiZv7VcxVqiMYmodxanr9fL/jZj8XsE0RBV i/fh4DqWF49c+4s4x2KgWCboxiQhMEUfHxSJK2asSXkYA2hMp4vFA3zWSxoerizlUFan oiHrkSPDUkBM8BeHOiuREzv7DQOoNW3ZXh8HGwRr7DWJ5NMwbvbIeKlATmeJoYkunqDQ ceuV5mkrwq/QKqf4bm0hhlPQEVq+0nodUc7RUbMOqoao2EZGWlALtl1mRmzy2SY9ulTg oWsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=CtbOxBtDQ8YKkBKoHAd6BN8kEl9MRNPz2T4pyCrciLE=; b=WW7B+uJXfAydP1jKQCFZEGIdEMgYXVkzkQILtf9c33nqjaLw8OY7VV3xIfR7Mb26mk BprBaAoXH7fKw2IUEC1l04Z4tjIo0iKu+AiChQe5YUjp2Uf9sRpO+DZmZtBkQomcKsNy YMWRpWHGn129XzSQTNijTpgUUku8MeveUeMeuc6IvG3sWHMIdvMwOp3knm41erToJ4ix x5MDhYNGromWiPVqW7jB/vRm8QCx1iH7WAgetXJ17kft3STB36wmJln2s0fYzTF98M+J g+mU01IODHDzunoFyJ0FgtvB0VlvRWiTuYuKWPREHwJRCGOexjlTxU71p6pm5PP6hCmu EJjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=S6qB1hgQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a24si15296345ejs.633.2020.07.07.22.03.42; Tue, 07 Jul 2020 22:04:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=S6qB1hgQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729493AbgGHFAU (ORCPT + 99 others); Wed, 8 Jul 2020 01:00:20 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:17582 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728542AbgGHFAS (ORCPT ); Wed, 8 Jul 2020 01:00:18 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 07 Jul 2020 22:00:05 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 07 Jul 2020 22:00:17 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 07 Jul 2020 22:00:17 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jul 2020 05:00:13 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jul 2020 05:00:13 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 07 Jul 2020 22:00:13 -0700 From: Krishna Reddy To: , , , , , CC: , , , , , , , , , , , , , , Krishna Reddy Subject: [PATCH v10 1/5] iommu/arm-smmu: move TLB timeout and spin count macros Date: Tue, 7 Jul 2020 22:00:13 -0700 Message-ID: <20200708050017.31563-2-vdumpa@nvidia.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200708050017.31563-1-vdumpa@nvidia.com> References: <20200708050017.31563-1-vdumpa@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594184405; bh=CtbOxBtDQ8YKkBKoHAd6BN8kEl9MRNPz2T4pyCrciLE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=S6qB1hgQ2DEiLBHH/f7WIcQiUQYQRxt91DEFQxDOgvoQNxnTXDcDFQh7pGNGpcMz1 2ei+CqcM4vFcCJXbuMOh6FWrlUWk0ZxPmlP3O6d/Gu45Cny/nJhVQ3nya6okn0ezjw 6UBXi/z5ZI69RT8Jv8hIv6R2sXx6Ycgzhc/JCKjgT+PirijgYHiIWf7W1AMXZbce/Y 1BCV1ZxqDEWRCwyuorr+xc+Qp0n7eZ3+eShXptPsW99c+50n/zhycapM06bytkwPy2 V8fYOA4Stl0xV5xbUBrTn7TbpFb3giNKjr/8vcL/cKv0wbV6U75zYx/RqBtwsh3kYT HZ/bvmiw4D5aw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move TLB timeout and spin count macros to header file to allow using the same from vendor specific implementations. Signed-off-by: Krishna Reddy --- drivers/iommu/arm-smmu.c | 3 --- drivers/iommu/arm-smmu.h | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 243bc4cb2705..d2054178df35 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -52,9 +52,6 @@ */ #define QCOM_DUMMY_VAL -1 =20 -#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ -#define TLB_SPIN_COUNT 10 - #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 =20 diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index d172c024be61..c7d0122a7c6c 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -236,6 +236,8 @@ enum arm_smmu_cbar_type { /* Maximum number of context banks per SMMU */ #define ARM_SMMU_MAX_CBS 128 =20 +#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ +#define TLB_SPIN_COUNT 10 =20 /* Shared driver definitions */ enum arm_smmu_arch_version { --=20 2.26.2