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Subject: Re: [PATCH] KVM: x86/mmu: Add capability to zap only sptes for the
 affected memslot
To:     Sean Christopherson <sean.j.christopherson@intel.com>
Cc:     Vitaly Kuznetsov <vkuznets@redhat.com>,
        Wanpeng Li <wanpengli@tencent.com>,
        Jim Mattson <jmattson@google.com>,
        Joerg Roedel <joro@8bytes.org>, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Xiong Zhang <xiong.y.zhang@intel.com>,
        Wayne Boyer <wayne.boyer@intel.com>,
        Zhenyu Wang <zhenyuw@linux.intel.com>,
        Jun Nakajima <jun.nakajima@intel.com>
References: <20200703025047.13987-1-sean.j.christopherson@intel.com>
From:   Paolo Bonzini <pbonzini@redhat.com>
Message-ID: <51637a13-f23b-8b76-c93a-76346b4cc982@redhat.com>
Date:   Wed, 8 Jul 2020 18:08:24 +0200
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On 03/07/20 04:50, Sean Christopherson wrote:
> Introduce a new capability, KVM_CAP_MEMSLOT_ZAP_CONTROL, to allow
> userspace to control the memslot zapping behavior on a per-VM basis.
> x86's default behavior is to zap all SPTEs, including the root shadow
> page, across all memslots.  While effective, the nuke and pave approach
> isn't exactly performant, especially for large VMs and/or VMs that
> heavily utilize RO memslots for MMIO devices, e.g. option ROMs.
> 
> On a vanilla VM with 6gb of RAM, the targeted zap reduces the number of
> EPT violations during boot by ~14% with THP enabled in the host, and by
> ~7% with THP disabled in the host.  On a much more custom VM with 32gb
> and a significant amount of memslot zapping, this can reduce the number
> of EPT violations by 50% during guest boot, and improve boot time by
> as much as 25%.
> 
> Keep the current x86 memslot zapping behavior as the default, as there's
> an unresolved bug that pops up when zapping only the affected memslot,
> and the exact conditions that trigger the bug are not fully known.  See
> https://patchwork.kernel.org/patch/10798453 for details.
> 
> Implement the capability as a set of flags so that other architectures
> might be able to use the capability without having to conform to x86's
> semantics.

It's bad that we have no clue what's causing the bad behavior, but I
don't think it's wise to have a bug that is known to happen when you
enable the capability. :/

Paolo