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[23.128.96.18]) by mx.google.com with ESMTP id m8si351828ejq.294.2020.07.08.10.48.09; Wed, 08 Jul 2020 10:48:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@cerno.tech header.s=fm3 header.b=bzzBa6oe; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=cRSrN+T+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=cerno.tech Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728255AbgGHRpE (ORCPT + 99 others); Wed, 8 Jul 2020 13:45:04 -0400 Received: from wnew4-smtp.messagingengine.com ([64.147.123.18]:32937 "EHLO wnew4-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727940AbgGHRoD (ORCPT ); Wed, 8 Jul 2020 13:44:03 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.west.internal (Postfix) with ESMTP id 533B72F3; Wed, 8 Jul 2020 13:44:02 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Wed, 08 Jul 2020 13:44:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=+opq7dviRqqbg 95K03jNnT1NFi4cLJAuYRa2X/OWjDw=; b=bzzBa6oeQ1s03foJvkL4KPXNH/AKF Hy3fAoSm4sgNEsEA5dW0TPcWoEt2SP9eMOmXlNzTsnpz3Ht/bxqNOcyE2FSyiqzE bu/E/BFBAUvj9Tc9a4/kUzFZGqzSNvA/kOaeKPKCm3PVeKA58jadfas/lMDWucOx pYfOychY3yNGsAVf2N6Be72FofA8PcRfBO4kZ1VfQCH18PLQmH5X7L4OQWk4cBEF 1JQtj6kbrVtPKbzReExm9QR5EBD/ii8f13vzLAYf4P2xTaIo8BpAk6GDAzKyOUEu uE76GhEiTYJktysZpaBrie0HtO8Rjyh5GrMJyj95WazeKcPHVL6WGdkgw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=+opq7dviRqqbg95K03jNnT1NFi4cLJAuYRa2X/OWjDw=; b=cRSrN+T+ 6K3ZWi+FKbka+D9Krde2hL9ZYbSuSAN7bP9sM7k4gajnWGPk5S//98Tx3895Fcme YTGAeO+QcVaS429EcZmlZaCTvgekOnM1aUiORTJIk3kzxNgfa52hBDwH/N8XUkzn BWQ14tPQQV9/MCk9qSUUuGHstKBQN6a3abVovFkWTd1t6CKJBXDFDDuAlE5el7t8 PJjVphN+l5LTSXcn6q4LVJ03GaFHmDG1huvYpSgFW5Fp1A9W5OR3fhZVgo43hq1N SLn7bGl7bHmg7IdHhJI8vmIyniwsi93/R2y/UOXOr3eg3yMKj2MGv72RD+RDWwa4 +pXYH1kyN77V+w== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduiedrudejgdduudejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeforgigihhm vgcutfhiphgrrhguuceomhgrgihimhgvsegtvghrnhhordhtvggthheqnecuggftrfgrth htvghrnhepvdekleevfeffkeejhfffueelteelfeduieefheduudfggffhhfffheevveeh hedvnecukfhppeeltddrkeelrdeikedrjeeinecuvehluhhsthgvrhfuihiivgepheekne curfgrrhgrmhepmhgrihhlfhhrohhmpehmrgigihhmvgestggvrhhnohdrthgvtghh X-ME-Proxy: Received: from localhost (lfbn-tou-1-1502-76.w90-89.abo.wanadoo.fr [90.89.68.76]) by mail.messagingengine.com (Postfix) with ESMTPA id 7D99130600A9; Wed, 8 Jul 2020 13:44:01 -0400 (EDT) From: Maxime Ripard To: Nicolas Saenz Julienne , Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tim Gover , Phil Elwell , Maxime Ripard Subject: [PATCH v4 63/78] drm/vc4: hdmi: Use clk_set_min_rate instead Date: Wed, 8 Jul 2020 19:42:11 +0200 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The HSM clock needs to be running at 101% the pixel clock of the HDMI controller, however it's shared between the two HDMI controllers, which means that if the resolutions are different between the two HDMI controllers, and the lowest resolution is on the second (in enable order) controller, the first HDMI controller will end up with a smaller than expected clock rate. Since we don't really need an exact frequency there, we can simply change the minimum rate we expect instead. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index 9f30fab744f2..d99188c90ff9 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -462,7 +462,7 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) * pixel clock, but HSM ends up being the limiting factor. */ hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); - ret = clk_set_rate(vc4_hdmi->hsm_clock, hsm_rate); + ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); if (ret) { DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); return; -- git-series 0.9.1