Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp755021ybt; Wed, 8 Jul 2020 10:50:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw/T+CAlaFZOa4kYGAFgpAr71Zs2+JbzpfHbPsHCbHLs0IKisPIJSaU/40bYR4NmhsYJfj4 X-Received: by 2002:aa7:d049:: with SMTP id n9mr62813607edo.39.1594230606894; Wed, 08 Jul 2020 10:50:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594230606; cv=none; d=google.com; s=arc-20160816; b=Zkow/dDAkwn7nymmF6cDmY1zwT/LQvaxtE8I4GvDuoCOhfLi9kO3nqhyT7p4TbA/Z6 8Z7ld80bEdW63bpyQzjpwrDjiNF+VfFf1eqEck9mGIKzLsfJq0AdihKv0q0QEoEF2z1q YUOuYBR9bK4PAoY+UtJuMbAnAyDjxICbFUpnuJhK9xqh4RoLuokPYZJ/xG2id32l7gBJ gxaTKkrnmpRuPpD+uBI1S9o57/bNfV0MbyeRZdSlAxgugMWIEtpULXkNnET765vYDbU0 EDlJrlogVOC8VAspXC0hpc6Psr0LLmRvl+1KDGaPI2AUH8ci4Nmeqxaw9xwGFnTQlEiY 5ubw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-signature; bh=4ovOYU6JzpFt/RYQbSmJy7CjmiXZoiogNvFC2X/3xU0=; b=J5MIO04SLhxvo6GtFF9vVH3WfKNk1LXK1fkwc0vAV397j1n1DgtDBGaTfLvzZMRkOy 9UXcfhEGt8AFmt6u7Ucpd91ojCODV+nSQUkcf5yyGXV+07XAdPJAzrFT/XCCYe26xZYN 6d4KN5mZJaTSVwlmMOvFhFFyT3MEJAjvti0qWNZkNLUIOQXpf4RwOSgwVuB+zd5JdW6c QvUOonBdKXvGRUqQ7djWIi1I7hEPmCYgTuI2XHZLrVXvxQLuE8A7OIYSdLWKR17hI+o5 QXSiBGKEB6CIgjxXY8p3xpdbG+KwVn5orgXquW7AYXr+cjRLogWHnNW/uuxOLJf1oL4E yGXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@cerno.tech header.s=fm3 header.b=mZJ6GAcA; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=nZSVm1s9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=cerno.tech Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id l23si351048ejq.14.2020.07.08.10.49.43; Wed, 08 Jul 2020 10:50:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@cerno.tech header.s=fm3 header.b=mZJ6GAcA; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=nZSVm1s9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=cerno.tech Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727065AbgGHRqT (ORCPT + 99 others); Wed, 8 Jul 2020 13:46:19 -0400 Received: from wnew4-smtp.messagingengine.com ([64.147.123.18]:45515 "EHLO wnew4-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726851AbgGHRnN (ORCPT ); Wed, 8 Jul 2020 13:43:13 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.west.internal (Postfix) with ESMTP id 0F4442F3; Wed, 8 Jul 2020 13:43:11 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Wed, 08 Jul 2020 13:43:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=4ovOYU6JzpFt/ RYQbSmJy7CjmiXZoiogNvFC2X/3xU0=; b=mZJ6GAcAHQg5fgX52WkiKirygWzD3 YwcQ2lJybVovSO1T35hRQv/WvNjeZk+WhU4zjWrCGv2ghMwyo364usdszeZ/WuE3 qmAJHHJhGspiqEwZHQkQH4/zwquzEfOjr0O4fAZ2ZJjtEzyGIJq7TXPZPKJ4wm6m Fq6aHAP3aHN7isf3/Zq9pq3vpYxYX8+JfPQSYrTI+qYajeC8KrpY9cC0fUdNq7iu wXYkk6atGey+6WPMhYKHoVbTPLVIbBKFvJniQyEB+lJC6oQnPdQ1huhQq3584H+G /ion6xIYAlsPZGb7gPFDJkEj2TyTDP2Xq0oodZRaTC3mahUvBtqFUWHvQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=4ovOYU6JzpFt/RYQbSmJy7CjmiXZoiogNvFC2X/3xU0=; b=nZSVm1s9 9oOrgi0z/FuWhONpYluANldea+10xM+Ff2HRpElBdQKYKQgSaOAx54g+3+P1c0RA Vm3MTmrcf8SdDF4dRkxyuuFuZN5RicoXG17YR3kEwd9w0XrxhnyCfEIn0y2TTH2g 0Pq6/dBn2co+hc23b4m/4rhLJ9HFnQ0idkyfvq730Xcda6E0UQ2Av038ddqGj8ce 2UZ4NLuj6DiwpgVcovWf9epE4ZcWnqmMrnVqzLlsQv5EM8vLCVhSMjFdiHKjPoky zQyqyljHZqED8gVokifnVd5KnEXhq7zR6PSl6roS2S0LnvNMMi3VJipeGfEgWzcY gKPaqFwkC3L9Ig== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduiedrudejgdduudejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeforgigihhm vgcutfhiphgrrhguuceomhgrgihimhgvsegtvghrnhhordhtvggthheqnecuggftrfgrth htvghrnhepvdekleevfeffkeejhfffueelteelfeduieefheduudfggffhhfffheevveeh hedvnecukfhppeeltddrkeelrdeikedrjeeinecuvehluhhsthgvrhfuihiivgepvdegne curfgrrhgrmhepmhgrihhlfhhrohhmpehmrgigihhmvgestggvrhhnohdrthgvtghh X-ME-Proxy: Received: from localhost (lfbn-tou-1-1502-76.w90-89.abo.wanadoo.fr [90.89.68.76]) by mail.messagingengine.com (Postfix) with ESMTPA id 4391C3280059; Wed, 8 Jul 2020 13:43:11 -0400 (EDT) From: Maxime Ripard To: Nicolas Saenz Julienne , Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tim Gover , Phil Elwell , Maxime Ripard Subject: [PATCH v4 28/78] drm/vc4: encoder: Add finer-grained encoder callbacks Date: Wed, 8 Jul 2020 19:41:36 +0200 Message-Id: <5fadf9256d130d447e3c66a0c86ceeba05c47fa4.1594230107.git-series.maxime@cerno.tech> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In the BCM2711, the setup of the HVS, pixelvalve and HDMI controller requires very precise ordering and timing that the regular atomic callbacks don't provide. Let's add new callbacks on top of the regular ones to be able to split the configuration as needed. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 19 +++++++++++++++++++ drivers/gpu/drm/vc4/vc4_drv.h | 7 +++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index b7b0e19e2fe1..d0b326e1df0a 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -389,6 +389,8 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, { struct drm_device *dev = crtc->dev; struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); + struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); int ret; require_hvs_enabled(dev); @@ -401,10 +403,16 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); + if (vc4_encoder->post_crtc_disable) + vc4_encoder->post_crtc_disable(encoder); + CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN); vc4_hvs_atomic_disable(crtc, old_state); + if (vc4_encoder->post_crtc_powerdown) + vc4_encoder->post_crtc_powerdown(encoder); + /* * Make sure we issue a vblank event after disabling the CRTC if * someone was waiting it. @@ -424,6 +432,8 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, { struct drm_device *dev = crtc->dev; struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); + struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); require_hvs_enabled(dev); @@ -434,15 +444,24 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, vc4_hvs_atomic_enable(crtc, old_state); + if (vc4_encoder->pre_crtc_configure) + vc4_encoder->pre_crtc_configure(encoder); + vc4_crtc_config_pv(crtc); CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN); + if (vc4_encoder->pre_crtc_enable) + vc4_encoder->pre_crtc_enable(encoder); + /* When feeding the transposer block the pixelvalve is unneeded and * should not be enabled. */ CRTC_WRITE(PV_V_CONTROL, CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN); + + if (vc4_encoder->post_crtc_enable) + vc4_encoder->post_crtc_enable(encoder); } static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index dfcc684f5d28..251fcc35530c 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -439,6 +439,13 @@ struct vc4_encoder { struct drm_encoder base; enum vc4_encoder_type type; u32 clock_select; + + void (*pre_crtc_configure)(struct drm_encoder *encoder); + void (*pre_crtc_enable)(struct drm_encoder *encoder); + void (*post_crtc_enable)(struct drm_encoder *encoder); + + void (*post_crtc_disable)(struct drm_encoder *encoder); + void (*post_crtc_powerdown)(struct drm_encoder *encoder); }; static inline struct vc4_encoder * -- git-series 0.9.1