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[216.228.112.21]) by smtp.gmail.com with ESMTPSA id y17sm577996pfe.30.2020.07.08.13.37.02 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Jul 2020 13:37:02 -0700 (PDT) Date: Wed, 8 Jul 2020 13:36:50 -0700 From: Nicolin Chen To: Krishna Reddy Cc: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, robh+dt@kernel.org, treding@nvidia.com, jonathanh@nvidia.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, yhsu@nvidia.com, snikam@nvidia.com, praithatha@nvidia.com, talho@nvidia.com, bbiswas@nvidia.com, mperttunen@nvidia.com, nicolinc@nvidia.com, bhuntsman@nvidia.com Subject: Re: [PATCH v10 3/5] iommu/arm-smmu: add NVIDIA implementation for ARM MMU-500 usage Message-ID: <20200708203648.GB28080@Asurada-Nvidia> References: <20200708050017.31563-1-vdumpa@nvidia.com> <20200708050017.31563-4-vdumpa@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200708050017.31563-4-vdumpa@nvidia.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 07, 2020 at 10:00:15PM -0700, Krishna Reddy wrote: > NVIDIA's Tegra194 SoC has three ARM MMU-500 instances. > It uses two of the ARM MMU-500s together to interleave IOVA > accesses across them and must be programmed identically. > This implementation supports programming the two ARM MMU-500s > that must be programmed identically. > > The third ARM MMU-500 instance is supported by standard > arm-smmu.c driver itself. > > Signed-off-by: Krishna Reddy Reviewed-by: Nicolin Chen