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Subject: Re: [PATCH v7 04/11] dmaengine: Introduce max SG list entries
 capability
To:     Serge Semin <Sergey.Semin@baikalelectronics.ru>,
        Vinod Koul <vkoul@kernel.org>,
        Viresh Kumar <vireshk@kernel.org>,
        Dan Williams <dan.j.williams@intel.com>
CC:     Serge Semin <fancer.lancer@gmail.com>,
        Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
        Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Arnd Bergmann <arnd@arndb.de>,
        Rob Herring <robh+dt@kernel.org>, <linux-mips@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <dmaengine@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
References: <20200709224550.15539-1-Sergey.Semin@baikalelectronics.ru>
 <20200709224550.15539-5-Sergey.Semin@baikalelectronics.ru>
From:   Peter Ujfalusi <peter.ujfalusi@ti.com>
Message-ID: <d667adda-6576-623d-6976-30f60ab3c3dc@ti.com>
Date:   Fri, 10 Jul 2020 11:31:47 +0300
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On 10/07/2020 1.45, Serge Semin wrote:
> Some devices may lack the support of the hardware accelerated SG list
> entries automatic walking through and execution. In this case a burden =
of
> the SG list traversal and DMA engine re-initialization lies on the
> DMA engine driver (normally implemented by using a DMA transfer complet=
ion
> IRQ to recharge the DMA device with a next SG list entry). But such
> solution may not be suitable for some DMA consumers. In particular SPI
> devices need both Tx and Rx DMA channels work synchronously in order
> to avoid the Rx FIFO overflow. In case if Rx DMA channel is paused for
> some time while the Tx DMA channel works implicitly pulling data into t=
he
> Rx FIFO, the later will be eventually overflown, which will cause the d=
ata
> loss. So if SG list entries aren't automatically fetched by the DMA
> engine, but are one-by-one manually selected for execution in the
> ISRs/deferred work/etc., such problem will eventually happen due to the=

> non-deterministic latencies of the service execution.

It is not really the number of sg nents which is the problem, but the
combination of total number of bytes _and_ the number of nents used to
map them.
Obviously the TX and RX number of bytes must match in duplex case and at
the same time neither nents should be over the number of SGs the DMA
device can handle without interruption (linking, chaining, or whatever
means).

The EDMA from TI have similar limitation (we set the limit to 20 nents).
Longer lists will be broken up to maximum of 20 segment transfers.
This setup has bigger impact on audio (cyclic) as we need to limit the
number of periods to not exceed this limit of 20.

The sDMA on the other hand has different limits. Earlier versions
without linking support can execute one SG chunk at the time and needs
to reconfigure for the next one -> max_sg_nents is 1 for the older sDMAs.=
=2E.

> In order to let the DMA consumer know about the DMA device capabilities=

> regarding the hardware accelerated SG list traversal we introduce the
> max_sg_list capability. It is supposed to be initialized by the DMA eng=
ine
> driver with 0 if there is no limitation for the number of SG entries
> atomically executed and with non-zero value if there is such constraint=
s,
> so the upper limit is determined by the number set to the property.
>=20
> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>=20
> ---
>=20
> Changelog v3:
> - This is a new patch created as a result of the discussion with Vinud =
and
>   Andy in the framework of DW DMA burst and LLP capabilities.
>=20
> Changelog v4:
> - Fix of->if typo. It should be definitely of.
> ---
>  drivers/dma/dmaengine.c   | 1 +
>  include/linux/dmaengine.h | 8 ++++++++
>  2 files changed, 9 insertions(+)
>=20
> diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
> index b332ffe52780..ad56ad58932c 100644
> --- a/drivers/dma/dmaengine.c
> +++ b/drivers/dma/dmaengine.c
> @@ -592,6 +592,7 @@ int dma_get_slave_caps(struct dma_chan *chan, struc=
t dma_slave_caps *caps)
>  	caps->directions =3D device->directions;
>  	caps->min_burst =3D device->min_burst;
>  	caps->max_burst =3D device->max_burst;
> +	caps->max_sg_nents =3D device->max_sg_nents;
>  	caps->residue_granularity =3D device->residue_granularity;
>  	caps->descriptor_reuse =3D device->descriptor_reuse;
>  	caps->cmd_pause =3D !!device->device_pause;
> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> index 0c7403b27133..a7e4d8dfdd19 100644
> --- a/include/linux/dmaengine.h
> +++ b/include/linux/dmaengine.h
> @@ -467,6 +467,9 @@ enum dma_residue_granularity {
>   *	should be checked by controller as well
>   * @min_burst: min burst capability per-transfer
>   * @max_burst: max burst capability per-transfer
> + * @max_sg_nents: max number of SG list entries executed in a single a=
tomic
> + *	DMA tansaction with no intermediate IRQ for reinitialization. Zero
> + *	value means unlimited number of entries.

Without looking at the comment the name max_sg_nents implies that the
DMA can not handle longer lists, but it is not really true.
max_sg_nents_burst might be a bit cleaner for the first look?

>   * @cmd_pause: true, if pause is supported (i.e. for reading residue o=
r
>   *	       for resume later)
>   * @cmd_resume: true, if resume is supported
> @@ -481,6 +484,7 @@ struct dma_slave_caps {
>  	u32 directions;
>  	u32 min_burst;
>  	u32 max_burst;
> +	u32 max_sg_nents;
>  	bool cmd_pause;
>  	bool cmd_resume;
>  	bool cmd_terminate;
> @@ -773,6 +777,9 @@ struct dma_filter {
>   *	should be checked by controller as well
>   * @min_burst: min burst capability per-transfer
>   * @max_burst: max burst capability per-transfer
> + * @max_sg_nents: max number of SG list entries executed in a single a=
tomic
> + *	DMA tansaction with no intermediate IRQ for reinitialization. Zero
> + *	value means unlimited number of entries.
>   * @residue_granularity: granularity of the transfer residue reported
>   *	by tx_status
>   * @device_alloc_chan_resources: allocate resources and return the
> @@ -844,6 +851,7 @@ struct dma_device {
>  	u32 directions;
>  	u32 min_burst;
>  	u32 max_burst;
> +	u32 max_sg_nents;
>  	bool descriptor_reuse;
>  	enum dma_residue_granularity residue_granularity;
> =20
>=20

- P=C3=A9ter

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