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Subject: Re: [PATCH v4 4/7] mtd: spi-nor: core: add configuration register 2 read & write
 support
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From:   masonccyang@mxic.com.tw
Date:   Mon, 13 Jul 2020 13:56:49 +0800
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+ YC Lin in loop,

--
> 
> Subject
> 
> [PATCH v4 4/7] mtd: spi-nor: core: add configuration register 2 read & 
write support
> 
> Configuration register 2 is to set the device operation condition like
> STR or DTR mode at address offset 0 and DQS mode at address offset 
0x200.
> 
> Each device has various address offset for it's specific operatoin
> setting.
> 
> Signed-off-by: Mason Yang <masonccyang@mxic.com.tw>
> ---


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