Date: Thu, 04 May 2006 15:51:25 -0700 (PDT)
Message-Id: <20060504.155125.68091905.davem@davemloft.net>
To: jengelh@linux01.gwdg.de
Cc: vda@ilport.com.ua, linux-kernel@vger.kernel.org
Subject: Re: www.softpanorama.org: sparc_vs_x86 fun
From: "David S. Miller" <davem@davemloft.net>
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From: Jan Engelhardt <jengelh@linux01.gwdg.de>
Date: Thu, 4 May 2006 13:31:37 +0200 (MEST)

> while on SPARC, it takes 6 instructions (of course, being RISC makes it 
> execute differently than x64)
> 
>     sethi %g1, $some_upper_bits
>     or %g1, $next_bitgroup
>     (shift-left)
>     or %g1, $next_bitgroup
>     (shift-left)
>     or %g1, $last_bitgroup
> 
> BTW, T1 is cool, but that the 1U version only has space for 1 disk is 
> pretty limiting :/

This example instruction sequence is incredibly misleading.

First of all, the vast majority of constants can be loaded in 1 to 3
instruction sequences.  I know this because I wrote the code that
emits 64-bit constant loading in the sparc backend of gcc and I've
watched how it tends to work when compiling real code.

Yes, the code density sucks on sparc compared to any x86 variant,
32-bit or 64-bit, but there is no need to exaggerate.

For symbolic references, it depends upon the code model and whether
you are generating PIC or not.  If you use the 32-bit medlow code
model, non-PIC, which is the default for apps being compiled under
sparc64/Linux, it's two instructions to load a symbol address.

The sequence gets progressively larger as you move onto the medmid
and midany code models.

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