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From:   Cheng-Yi Chiang <cychiang@chromium.org>
To:     linux-kernel@vger.kernel.org
Cc:     Taniya Das <tdas@codeaurora.org>,
        Rohit kumar <rohitkr@codeaurora.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>, dianders@chromium.org,
        linux-arm-kernel@lists.infradead.org,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        Ajit Pandey <ajitp@codeaurora.org>,
        Cheng-Yi Chiang <cychiang@chromium.org>
Subject: [PATCH] arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driver
Date:   Thu, 16 Jul 2020 14:14:45 +0800
Message-Id: <20200716061445.628709-1-cychiang@chromium.org>
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From: Ajit Pandey <ajitp@codeaurora.org>

Add the I2S controller node to sc7180 dtsi.
Add pinmux for pirmary and secondary I2S.

Signed-off-by: Ajit Pandey <ajitp@codeaurora.org>
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
---
This patch depends on these patch series so it is not ready to be merged now.
- clk: qcom: Support for Low Power Audio Clocks on SC7180 https://patchwork.kernel.org/cover/11664273/
- arm64: dts: qcom: sc7180: Add LPASS clock controller nodes https://patchwork.kernel.org/patch/11664303/
- ASoC: qcom: Add support for SC7180 lpass variant https://patchwork.kernel.org/cover/11650649/

 arch/arm64/boot/dts/qcom/sc7180.dtsi | 132 +++++++++++++++++++++++++++
 1 file changed, 132 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 6eb14b6a47f5..2fe3bd89f950 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -511,6 +511,34 @@ qusb2p_hstx_trim: hstx-trim-primary@25b {
 			};
 		};
 
+		lpass_cpu: lpass {
+			compatible = "qcom,lpass-cpu-sc7180";
+
+			reg = <0 0x62F00000 0 0x29000>;
+			reg-names = "lpass-lpaif";
+
+			iommus = <&apps_smmu 0x1020 0>;
+
+			power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
+
+			status = "disabled";
+
+			clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
+				 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
+				 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
+				 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
+				 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
+				 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
+
+			clock-names = "noc", "audio-core", "mclk0", "sysnoc_mport",
+				      "pri_ibit", "sec_ibit";
+
+			#sound-dai-cells = <1>;
+
+			interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "lpass-irq-lpaif";
+		};
+
 		sdhc_1: sdhci@7c4000 {
 			compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0 0x7c4000 0 0x1000>,
@@ -1357,6 +1385,110 @@ pinmux {
 				};
 			};
 
+			sec_mi2s_active: sec-mi2s-active {
+				pinmux {
+					pins = "gpio49";
+					function = "mi2s_1";
+				};
+
+				pinconf {
+					pins = "gpio49";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
+
+			sec_mi2s_ws_active: sec-mi2s-ws-active {
+				pinmux {
+					pins = "gpio50";
+					function = "mi2s_1";
+				};
+
+				pinconf {
+					pins = "gpio50";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
+
+			sec_mi2s_dout_active: sec-mi2s-dout-active {
+				pinmux {
+					pins = "gpio51";
+					function = "mi2s_1";
+				};
+
+				pinconf {
+					pins = "gpio51";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
+
+			pri_mi2s_active: pri-mi2s-active {
+				pinmux {
+					pins = "gpio53";
+					function = "mi2s_0";
+				};
+
+				pinconf {
+					pins = "gpio53";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
+
+			pri_mi2s_ws_active: pri-mi2s-ws-active {
+				pinmux {
+					pins = "gpio54";
+					function = "mi2s_0";
+				};
+
+				pinconf {
+					pins = "gpio54";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
+
+			pri_mi2s_dout_active: pri-mi2s-dout-active {
+				pinmux {
+					pins = "gpio55";
+					function = "mi2s_0";
+				};
+
+				pinconf {
+					pins = "gpio55";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
+
+			pri_mi2s_din_active: pri-mi2s-din-active {
+				pinmux {
+					pins = "gpio56";
+					function = "mi2s_0";
+				};
+
+				pinconf {
+					pins = "gpio56";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
+
+			pri_mi2s_mclk_active: pri-mi2s-mclk-active {
+				pinmux {
+					pins = "gpio57";
+					function = "lpass_ext";
+				};
+
+				pinconf {
+					pins = "gpio57";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
+
 			sdc1_on: sdc1-on {
 				pinconf-clk {
 					pins = "sdc1_clk";
-- 
2.28.0.rc0.105.gf9edc3c819-goog