Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Subject: Re: [RFC PATCH v3 16/18] gpu: host1x: mipi: Split
 tegra_mipi_calibrate and tegra_mipi_wait
To:     Sowjanya Komatineni <skomatineni@nvidia.com>,
        thierry.reding@gmail.com, jonathanh@nvidia.com, frankc@nvidia.com,
        hverkuil@xs4all.nl, sakari.ailus@iki.fi, robh+dt@kernel.org,
        helen.koike@collabora.com
Cc:     sboyd@kernel.org, gregkh@linuxfoundation.org,
        linux-media@vger.kernel.org, devicetree@vger.kernel.org,
        linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-i2c@vger.kernel.org
References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com>
 <1594786855-26506-17-git-send-email-skomatineni@nvidia.com>
From:   Dmitry Osipenko <digetx@gmail.com>
Message-ID: <a06dec8f-7042-767b-545b-048685a7683d@gmail.com>
Date:   Thu, 16 Jul 2020 23:38:27 +0300
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101
 Thunderbird/68.10.0
MIME-Version: 1.0
In-Reply-To: <1594786855-26506-17-git-send-email-skomatineni@nvidia.com>
Content-Type: text/plain; charset=utf-8
Content-Language: en-US
Content-Transfer-Encoding: 8bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

15.07.2020 07:20, Sowjanya Komatineni пишет:
> SW can trigger MIPI pads calibration any time after power on
> but calibration results will be latched and applied to the pads
> by MIPI CAL unit only when the link is in LP-11 state and then
> status register will be updated.
> 
> For CSI, trigger of pads calibration happen during CSI stream
> enable where CSI receiver is kept ready prior to sensor or CSI
> transmitter stream start.
> 
> So, pads may not be in LP-11 at this time and waiting for the
> calibration to be done immediate after calibration start will
> result in timeout.
> 
> This patch splits tegra_mipi_calibrate() and tegra_mipi_wait()
> so triggering for calibration and waiting for it to complete can
> happen at different stages.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
...
>  int tegra_mipi_calibrate(struct tegra_mipi_device *device)
>  {
> @@ -370,12 +381,10 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device)
>  	value |= MIPI_CAL_CTRL_START;
>  	tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
>  
> -	err = tegra_mipi_wait(device->mipi);

Doesn't MIPI clock need to be enabled during of the calibration process?

>  	mutex_unlock(&device->mipi->lock);
>  	clk_disable(device->mipi->clk);
>  
> -	return err;
> +	return 0;
>  }
>  EXPORT_SYMBOL(tegra_mipi_calibrate);