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Subject: Re: [RFC PATCH v3 16/18] gpu: host1x: mipi: Split
 tegra_mipi_calibrate and tegra_mipi_wait
To:     Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
        <jonathanh@nvidia.com>, <frankc@nvidia.com>, <hverkuil@xs4all.nl>,
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From:   Sowjanya Komatineni <skomatineni@nvidia.com>
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Date:   Thu, 16 Jul 2020 15:49:35 -0700
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On 7/16/20 2:18 PM, Dmitry Osipenko wrote:
> 17.07.2020 00:09, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
>> On 7/16/20 1:38 PM, Dmitry Osipenko wrote:
>>> 15.07.2020 07:20, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
>>>> SW can trigger MIPI pads calibration any time after power on
>>>> but calibration results will be latched and applied to the pads
>>>> by MIPI CAL unit only when the link is in LP-11 state and then
>>>> status register will be updated.
>>>>
>>>> For CSI, trigger of pads calibration happen during CSI stream
>>>> enable where CSI receiver is kept ready prior to sensor or CSI
>>>> transmitter stream start.
>>>>
>>>> So, pads may not be in LP-11 at this time and waiting for the
>>>> calibration to be done immediate after calibration start will
>>>> result in timeout.
>>>>
>>>> This patch splits tegra_mipi_calibrate() and tegra_mipi_wait()
>>>> so triggering for calibration and waiting for it to complete can
>>>> happen at different stages.
>>>>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>> ...
>>>>  =C2=A0 int tegra_mipi_calibrate(struct tegra_mipi_device *device)
>>>>  =C2=A0 {
>>>> @@ -370,12 +381,10 @@ int tegra_mipi_calibrate(struct
>>>> tegra_mipi_device *device)
>>>>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 value |=3D MIPI_CAL_CTRL_START;
>>>>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tegra_mipi_writel(device->mipi, value,=
 MIPI_CAL_CTRL);
>>>>  =C2=A0 -=C2=A0=C2=A0=C2=A0 err =3D tegra_mipi_wait(device->mipi);
>>> Doesn't MIPI clock need to be enabled during of the calibration process=
?
>> MIPI clock is already enabled in tegra_mipi_calibrate
>>>>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mutex_unlock(&device->mipi->lock);
>>>>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clk_disable(device->mipi->clk);
> What keeps MIPI clock enabled after completion of the
> tegra_mipi_calibrate() invocation?

MIPI clock is disabled at end of tegra_mipi_calibrate and is re-enabled=20
during tegra_mipi_wait.

I think I should fix this to keep the clock enabled till calibration=20
results are latched.

All consumers of tegra_mipi_calibrate() will call tegra_mipi_wait().

So will remove clk_disable mipi clk at end of tegra_mipi_calibrate() and=20
clk_enable mipi_clk at beginning of tegra_mipi_wait()

>
>>>>  =C2=A0 -=C2=A0=C2=A0=C2=A0 return err;
>>>> +=C2=A0=C2=A0=C2=A0 return 0;
>>>>  =C2=A0 }
>>>>  =C2=A0 EXPORT_SYMBOL(tegra_mipi_calibrate);