Received: by 2002:a25:e74b:0:0:0:0:0 with SMTP id e72csp1680448ybh; Thu, 16 Jul 2020 20:30:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzzX8naIac6bFrVaILUtQ0MD4sKQErsBUlTx5Ws6vsZ2Kil1hjjPSPeqeA7a40TBVAZ21V7 X-Received: by 2002:a17:906:7283:: with SMTP id b3mr6977729ejl.163.1594956628959; Thu, 16 Jul 2020 20:30:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594956628; cv=none; d=google.com; s=arc-20160816; b=BR9v+zJPYidOfm8dB7GvFQ4Fb34ZpQtZt7iF50iQJmkHsNCma3LNESIBM59dyJvH3d vUVoNvLx4EkHDhFLFf00FleX5sBkDNJpOMKYFOED+DBALRAxsoOFqenUcUSaa55N1n47 cwHFEu5dNXpqNAbm2GFRBbp6cyx0TBOP4HQkkscEeMjLPHcmTgoe0IV1C/iW1P+3+gof Mydl6q+QWF8i7fBsvnzM/g+nKRrNMTBfccmEdA5RLbeQ3jzyQ3rhGOLh4LRw5G7f7mdv PpNGHIt0gHfzg9Z24oDpdWx/w3eEuQCRvy1EGAnhRvXGybzQmtYdKk2/8TkcvEfaHPoa J2EA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=m86oURK2effsy3cn1rTRJkebCIYjtIPpe7qNBEqgm78=; b=OyO0qrUm81SemnMQtvFMe88W7VHSXpTH8G2zdT8Q6xO7Z4d4LeOv2lZ0nbLE9/03FI iELCGHxhMEzjlWtMh7U8+Pg9nXkim93yAdDVbIpaIS5GzMmk1iyPRrlSBXskyf2j/AuS EvbTbAl2OqDEws9pQ/SCApqfi8zV6dCoW3qiEr9FpLPEd4s9of/N9ESPTOWiOt9wP/n6 2WJtv1aLUlTNiqmbFBrnXA0VRo0IG8zhWLhV3EgHn5AweDbvPAB9m4JYKR5UjroMA+ZZ coBwcGf20cuhOa52Uauja2zdnZ92u3/oFtgWni+pxcE5LYJMz2ee01imdmz/pYhsVbU8 j2aw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p11si4513487edq.445.2020.07.16.20.30.06; Thu, 16 Jul 2020 20:30:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727062AbgGQD1X (ORCPT + 99 others); Thu, 16 Jul 2020 23:27:23 -0400 Received: from lucky1.263xmail.com ([211.157.147.130]:37866 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727025AbgGQD1W (ORCPT ); Thu, 16 Jul 2020 23:27:22 -0400 Received: from localhost (unknown [192.168.167.13]) by lucky1.263xmail.com (Postfix) with ESMTP id AFE1CCA6B3; Fri, 17 Jul 2020 11:27:18 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P17843T139819831256832S1594956437744238_; Fri, 17 Jul 2020 11:27:18 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <1ed047bdfaf1ccd223d9c731b884a94b> X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Cc: linux-gpio@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kever.yang@rock-chips.com, david.wu@rock-chips.com, Jianqun Xu Subject: [PATCH 10/13] pinctrl: rockchip: Add RK3288 definitions to separate from other SoCs Date: Fri, 17 Jul 2020 11:27:16 +0800 Message-Id: <20200717032716.18331-1-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com> References: <20200717032411.17654-1-jay.xu@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add RK3288 definitions to separate from other SoCs. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index ec6a1a08f8b1..04e7027ec8e1 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1855,6 +1855,11 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, } #define RK3288_PULL_OFFSET 0x140 +#define RK3288_PULL_PMU_OFFSET 0x64 +#define RK3288_PULL_BITS_PER_PIN 2 +#define RK3288_PULL_PINS_PER_REG 8 +#define RK3288_PULL_BANK_STRIDE 16 + static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) @@ -1864,22 +1869,22 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, /* The first 24 pins of the first bank are located in PMU */ if (bank->bank_num == 0) { *regmap = info->regmap_pmu; - *reg = RK3188_PULL_PMU_OFFSET; + *reg = RK3288_PULL_PMU_OFFSET; - *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); - *bit = pin_num % RK3188_PULL_PINS_PER_REG; - *bit *= RK3188_PULL_BITS_PER_PIN; + *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3288_PULL_PINS_PER_REG; + *bit *= RK3288_PULL_BITS_PER_PIN; } else { *regmap = info->regmap_base; *reg = RK3288_PULL_OFFSET; /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; - *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; - *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + *reg += bank->bank_num * RK3288_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4); - *bit = (pin_num % RK3188_PULL_PINS_PER_REG); - *bit *= RK3188_PULL_BITS_PER_PIN; + *bit = (pin_num % RK3288_PULL_PINS_PER_REG); + *bit *= RK3288_PULL_BITS_PER_PIN; } } -- 2.17.1