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Date:   Fri, 17 Jul 2020 11:11:05 +0200
From:   Alexandre Belloni <alexandre.belloni@bootlin.com>
To:     Claudiu Beznea <claudiu.beznea@microchip.com>
Cc:     mturquette@baylibre.com, sboyd@kernel.org,
        nicolas.ferre@microchip.com, ludovic.desroches@microchip.com,
        bbrezillon@kernel.org, linux-kernel@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 03/19] clk: at91: clk-sam9x60-pll: fix mul mask
Message-ID: <20200717091105.GK3428@piout.net>
References: <1594812267-6697-1-git-send-email-claudiu.beznea@microchip.com>
 <1594812267-6697-4-git-send-email-claudiu.beznea@microchip.com>
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On 15/07/2020 14:24:11+0300, Claudiu Beznea wrote:
> According to datasheet mul mask is on bits 31..24.
> 
> Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

> ---
>  drivers/clk/at91/clk-sam9x60-pll.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index e699803986e5..3522eae2edd6 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -15,7 +15,7 @@
>  #include "pmc.h"
>  
>  #define	PMC_PLL_CTRL0_DIV_MSK	GENMASK(7, 0)
> -#define	PMC_PLL_CTRL1_MUL_MSK	GENMASK(30, 24)
> +#define	PMC_PLL_CTRL1_MUL_MSK	GENMASK(31, 24)
>  
>  #define PLL_DIV_MAX		(FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
>  #define UPLL_DIV		2
> -- 
> 2.7.4
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com