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From:   "Eads, Gage" <gage.eads@intel.com>
To:     Greg KH <gregkh@linuxfoundation.org>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "arnd@arndb.de" <arnd@arndb.de>,
        "Karlsson, Magnus" <magnus.karlsson@intel.com>,
        "Topel, Bjorn" <bjorn.topel@intel.com>
Subject: RE: [PATCH 01/20] dlb2: add skeleton for DLB 2.0 driver
Thread-Topic: [PATCH 01/20] dlb2: add skeleton for DLB 2.0 driver
Thread-Index: AQHWWGUNTth4ik4BzU63g7CSJsQmkakKy9cw
Date:   Fri, 17 Jul 2020 18:19:14 +0000
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> -----Original Message-----
> From: Greg KH <gregkh@linuxfoundation.org>
> Sent: Sunday, July 12, 2020 10:57 AM
> To: Eads, Gage <gage.eads@intel.com>
> Cc: linux-kernel@vger.kernel.org; arnd@arndb.de; Karlsson, Magnus
> <magnus.karlsson@intel.com>; Topel, Bjorn <bjorn.topel@intel.com>
> Subject: Re: [PATCH 01/20] dlb2: add skeleton for DLB 2.0 driver
>=20
> On Sun, Jul 12, 2020 at 08:43:12AM -0500, Gage Eads wrote:
> > +config INTEL_DLB2
> > +       tristate "Intel(R) Dynamic Load Balancer 2.0 Driver"
> > +       depends on 64BIT && PCI && X86
>=20
> Why just that platform?  What about CONFIG_TEST for everything else?

This device will only appear on an x86 platform. CONFIG_COMPILE_TEST won't =
work, since the driver uses the x86-only function iosubmit_cmds512().

>=20
> > +       help
> > +         This driver supports the Intel(R) Dynamic Load Balancer 2.0 (=
DLB 2.0)
> > +         device.
>=20
> Are you sure you need the (R) in Kconfig texts everywhere?

The second is probably overkill. Just the first one is required.

>=20
> And a bit more info here would be nice, as no one knows if they have this=
 or
> not, right?

Intel hasn't yet announced more information that I can include here. For no=
w, "lspci -d 8086:2710" will tell the user if this device is present.

>=20
> > --- /dev/null
> > +++ b/drivers/misc/dlb2/dlb2_hw_types.h
> > @@ -0,0 +1,29 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
>=20
> Why dual licensed?  I thought that Intel told me they were not going to d=
o
> that anymore for any kernel code going forward as it was just such a pain=
 and
> never actually helped anything.  Has that changed?
>=20

The driver is mostly GPLv2-only, but a subset constitutes a "hardware acces=
s library" that is almost completely OS-independent. "almost" because it ha=
s calls to non-GPL symbols like kmalloc() and kfree(). This dual-licensed p=
ortion can be ported to other environments that need the more permissive BS=
D license.

For the broader policy question, Intel's open source team will get back to =
you on this.

>=20
> > + * Copyright(c) 2016-2020 Intel Corporation */
> > +
> > +#ifndef __DLB2_HW_TYPES_H
> > +#define __DLB2_HW_TYPES_H
> > +
> > +#define DLB2_MAX_NUM_VDEVS 16
> > +#define DLB2_MAX_NUM_DOMAINS 32
> > +#define DLB2_MAX_NUM_LDB_QUEUES 32 /* LDB =3D=3D load-balanced */
> #define
> > +DLB2_MAX_NUM_DIR_QUEUES 64 /* DIR =3D=3D directed */ #define
> > +DLB2_MAX_NUM_LDB_PORTS 64 #define DLB2_MAX_NUM_DIR_PORTS
> > +DLB2_MAX_NUM_DIR_QUEUES #define DLB2_MAX_NUM_LDB_CREDITS
> 8192 #define
> > +DLB2_MAX_NUM_DIR_CREDITS 2048 #define
> DLB2_MAX_NUM_HIST_LIST_ENTRIES
> > +2048 #define DLB2_MAX_NUM_AQED_ENTRIES 2048 #define
> > +DLB2_MAX_NUM_QIDS_PER_LDB_CQ 8 #define
> > +DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS 2 #define
> > +DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES 5 #define
> DLB2_QID_PRIORITIES 8
> > +#define DLB2_NUM_ARB_WEIGHTS 8 #define DLB2_MAX_WEIGHT 255
> #define
> > +DLB2_NUM_COS_DOMAINS 4 #define DLB2_MAX_CQ_COMP_CHECK_LOOPS
> 409600
> > +#define DLB2_MAX_QID_EMPTY_CHECK_LOOPS (32 * 64 * 1024 * (800 / 30))
> > +#define DLB2_HZ 800000000
>=20
> No tabs?  How easy is that to read?  :(

I'll improve this (and a few other instances in later patches) in V2.

Thanks,
Gage

>=20
> greg k-h