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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id x9sm7088652pfq.11.2020.07.18.00.16.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jul 2020 00:16:53 -0700 (PDT) Date: Sat, 18 Jul 2020 00:16:50 -0700 From: Bjorn Andersson To: Shaik Sajida Bhanu Cc: adrian.hunter@intel.com, ulf.hansson@linaro.org, robh+dt@kernel.org, mka@chromium.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, agross@kernel.org, Pradeep P V K Subject: Re: [PATCH V1] arm64: dts: qcom: Add bandwidth votes for eMMC and SDcard Message-ID: <20200718071650.GC61202@yoga> References: <1595054006-6803-1-git-send-email-sbhanu@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1595054006-6803-1-git-send-email-sbhanu@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri 17 Jul 23:33 PDT 2020, Shaik Sajida Bhanu wrote: Plase add "sc7180: " between "qcom:" and "Add" > From: Pradeep P V K > > Add the bandwidth domain supporting performance state and > the corresponding OPP tables for the sdhc device on sc7180. > You need Pradeep's signed-off-by here before yours. > Signed-off-by: Shaik Sajida Bhanu > --- > This change is depends on the patch series > https://lkml.org/lkml/2020/6/30/1280 > Also depends on documentation commit 557ed5f (Present on linux-next) Afaict both of these exists in linux-next, so no need to mention them. Would be nice to have Rajendra's ack/reviewed-by on this patch, as you're amending his. Please Cc him. The change itself looks good to me though. Regards, Bjorn > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index 68f9894..d78a066 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -684,6 +684,9 @@ > clocks = <&gcc GCC_SDCC1_APPS_CLK>, > <&gcc GCC_SDCC1_AHB_CLK>; > clock-names = "core", "iface"; > + interconnects = <&aggre1_noc MASTER_EMMC &mc_virt SLAVE_EBI1>, > + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_EMMC_CFG>; > + interconnect-names = "sdhc-ddr","cpu-sdhc"; > power-domains = <&rpmhpd SC7180_CX>; > operating-points-v2 = <&sdhc1_opp_table>; > > @@ -704,11 +707,15 @@ > opp-100000000 { > opp-hz = /bits/ 64 <100000000>; > required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <100000 100000>; > + opp-avg-kBps = <100000 50000>; > }; > > opp-384000000 { > opp-hz = /bits/ 64 <384000000>; > required-opps = <&rpmhpd_opp_svs_l1>; > + opp-peak-kBps = <600000 900000>; > + opp-avg-kBps = <261438 300000>; > }; > }; > }; > @@ -2476,6 +2483,10 @@ > clocks = <&gcc GCC_SDCC2_APPS_CLK>, > <&gcc GCC_SDCC2_AHB_CLK>; > clock-names = "core", "iface"; > + > + interconnects = <&aggre1_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, > + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; > + interconnect-names = "sdhc-ddr","cpu-sdhc"; > power-domains = <&rpmhpd SC7180_CX>; > operating-points-v2 = <&sdhc2_opp_table>; > > @@ -2489,11 +2500,15 @@ > opp-100000000 { > opp-hz = /bits/ 64 <100000000>; > required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <160000 100000>; > + opp-avg-kBps = <80000 50000>; > }; > > opp-202000000 { > opp-hz = /bits/ 64 <202000000>; > required-opps = <&rpmhpd_opp_svs_l1>; > + opp-peak-kBps = <200000 120000>; > + opp-avg-kBps = <100000 60000>; > }; > }; > }; > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >