Received: by 2002:a25:e74b:0:0:0:0:0 with SMTP id e72csp238068ybh; Sat, 18 Jul 2020 02:23:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxxsBjIQSClclaYBDkYYd9DGMqTmLBOPPHocttHKdNC4h9vCsvfH64BqVlRERUtNkcPzADZ X-Received: by 2002:a05:6402:1544:: with SMTP id p4mr13214751edx.334.1595064192097; Sat, 18 Jul 2020 02:23:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595064192; cv=none; d=google.com; s=arc-20160816; b=J8FQxzy8cYjvg2AGTGg9ZPcsMolqDb0ClBxQkTLJt3MbKzwkA1X7O1slPfnIVXESw9 SXHToQCh7xB/hquHv2HDtiqDQZJK3SYqoggfJ+xQmni1WNF3cNmzJLrL6QHfebOHxd87 odu0SmvnHs80I5h+UaFFWY5Gcky2yeVV3Q7X3UfPLHpQ0jTRObr/dyBLBw8PqXbKeVwZ FDj+c/W4E90bjD7vjjrvCSm8Hb/+qbBHPgEPgdsB7EKyxHS/YxQkdeEUzFGvGl9Kzxgb S1JwG/xP13jkdUbOEYoJ2ZsdsB1LZwmcDU0c1ZqgOtYOASOk2ye3uaEb4lHLu/FxEvnx 9dOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=0LdVF4Wtif0/2NJuxoxJqSPIuVVPOku/Ym0I0U/TYRQ=; b=Kg13+PrGa2OfOl3psWKyfWbVFT2vfnCd8nttufVuLC3m50dQS8a+07W+6NzW0Ez2fE 7aaLvE1Qb0nsf+ULqASMBy6Ps4pqj71eYE+aCEYFJOv4tuGMqwQRgixlKfZlg5f6RFPC jSbtWRZo1Dt0W+ZkGC4snVmcaNNVujCp5JDN7lV8s7ynA0Uxc85wTSoTe499/sZkIdp/ iSf12D+q1kxzQxOadLvygx07D5+eOAUMIGrHL4Ev0gaJz68xiEpHocL5LN3iw3xP0h1m 1FcSv57wGnVw2bsVXPv+NLVMmV5DpjlRUHIiEW6d8LLkT1lDna6QGZqpoBvVuC/MkYDf F1iA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=qF1a1WZq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v5si6567828edl.202.2020.07.18.02.22.49; Sat, 18 Jul 2020 02:23:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=qF1a1WZq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726678AbgGRJUZ (ORCPT + 99 others); Sat, 18 Jul 2020 05:20:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726055AbgGRJUY (ORCPT ); Sat, 18 Jul 2020 05:20:24 -0400 Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9153C0619D2 for ; Sat, 18 Jul 2020 02:20:24 -0700 (PDT) Received: by mail-pf1-x442.google.com with SMTP id z3so6563874pfn.12 for ; Sat, 18 Jul 2020 02:20:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0LdVF4Wtif0/2NJuxoxJqSPIuVVPOku/Ym0I0U/TYRQ=; b=qF1a1WZqxZb+/GM7u9xwaCK8MPhe+9C27Lg/Z1kC+uAUQJEk1giMzh9GDXGvCzcWJP mcblQmc75BaJmzdim//KiDAJjR17Xo5NkB1n2ow3GpFxPtbppz3XeFm9jD8pOJqNdDVI ncI7ZTIsdeviSOEx+9hneHaYxHa+xjwMPWbae938fTO1XxFvuZqdZB4gxs2aMcsT49at w6Uaw/hbDDn+JKCrv2cGXfRGhXL2C6noOqF9R5HcethWFAN36B3HFejrh6rVgVYJp8HK Sf3sPg4MCDRJL4Ty1d7WeSu52f3wt7x6eY7PYznwL3DxR4OFKT91qPSues7/DAk2oHt4 wMzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0LdVF4Wtif0/2NJuxoxJqSPIuVVPOku/Ym0I0U/TYRQ=; b=M3MYZDJ/yxRtBdCYJMJQH5HXH9D6ANBL/smFL5f5ZVGgprBM0i8qjIKjE74pWMREse En/J16KTomUdOV52fY79O/uLCpo1LUxw1neJhSeWVLhEoyCy+72Ty0pCtPQcPevyd1tl S0JfTXfI49JZVHgZLNv398DE7SiMpT4hra+DPD+05YPzEerBAj2/Jb1TGNhJSwg6UANs SQzthIXCT9o+bU3CA2pmaewV74WGTXQdjJeOPDKwHx4aMDeqCAQ7hf73D5kaETW37lFo ANMhvlt1F+DnDeT6Lb06KfznWm/J9bMWlylEHswDzKBs6evCNtUQbicUCU9ofwripNaY kEdw== X-Gm-Message-State: AOAM5312mKSv0o08CHDEe0fskd2eTIghPaFhqAfMXkxIdSkf8VfwzXHh NRHcByR4eFBdSu7YGcbaqwk= X-Received: by 2002:a63:6486:: with SMTP id y128mr11297854pgb.82.1595064024179; Sat, 18 Jul 2020 02:20:24 -0700 (PDT) Received: from localhost.localdomain ([182.69.248.222]) by smtp.gmail.com with ESMTPSA id nl5sm5217800pjb.36.2020.07.18.02.20.18 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 18 Jul 2020 02:20:23 -0700 (PDT) From: Amit Singh Tomar To: andre.przywara@arm.com, afaerber@suse.de, manivannan.sadhasivam@linaro.org, sboyd@kernel.org Cc: cristian.ciocaltea@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org Subject: [PATCH v6 04/10] clk: actions: Add MMC clock-register reset bits Date: Sat, 18 Jul 2020 14:49:28 +0530 Message-Id: <1595063974-24228-5-git-send-email-amittomer25@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595063974-24228-1-git-send-email-amittomer25@gmail.com> References: <1595063974-24228-1-git-send-email-amittomer25@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This commit adds reset bits needed for MMC clock registers present on Actions S700 SoC. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Amit Singh Tomar --- Changes since v5: * Added Mani's Reviewed-by: tag. Changes from v4: * Reordered it from 03/10 to 04/10. Changes from v3: * NO change. Changes from v2: * No change. Changes from v1: * No change. Changes from RFC: * No change. --- drivers/clk/actions/owl-s700.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c index a2f34d13fb54..cd60eca7727d 100644 --- a/drivers/clk/actions/owl-s700.c +++ b/drivers/clk/actions/owl-s700.c @@ -577,6 +577,9 @@ static const struct owl_reset_map s700_resets[] = { [RESET_DSI] = { CMU_DEVRST0, BIT(2) }, [RESET_CSI] = { CMU_DEVRST0, BIT(13) }, [RESET_SI] = { CMU_DEVRST0, BIT(14) }, + [RESET_SD0] = { CMU_DEVRST0, BIT(22) }, + [RESET_SD1] = { CMU_DEVRST0, BIT(23) }, + [RESET_SD2] = { CMU_DEVRST0, BIT(24) }, [RESET_I2C0] = { CMU_DEVRST1, BIT(0) }, [RESET_I2C1] = { CMU_DEVRST1, BIT(1) }, [RESET_I2C2] = { CMU_DEVRST1, BIT(2) }, -- 2.7.4