Received: by 2002:a25:e74b:0:0:0:0:0 with SMTP id e72csp1620718ybh; Mon, 20 Jul 2020 03:05:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz+EbMJnjcE/renk7ZC6oxYoBlRp8y933xC0bx7cFmsySg/ZMq2nc4lDxOmE1A92Zgq6zNX X-Received: by 2002:a05:6402:1507:: with SMTP id f7mr21582101edw.37.1595239504378; Mon, 20 Jul 2020 03:05:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595239504; cv=none; d=google.com; s=arc-20160816; b=k1EyqiB80cUjMa1rlZCXjiMk4zk6bWp1auNUvAl3Pa2eif39b8XZKWeJRyvyMMhi52 no021NuOqBmTbZIkkjS6JgY/pdEWtOjszjPO2UAkWJTEcrnEmsy5kzGPbcbA8RXoXr7Y cCSJvQjaNCoAcVzeymGoF3pQjZ0K61a3Z6UQiKCORsqD7Vp6f5n1VyxdKAjLSVlj36zk R786/19VAoRekY7SRTVdHCOqUrnbOUy4JIOJhivk8zZSJEYnFq1lVsYyGf7CoVfNwQVk P5xEHFip2hmlql7+CN8tbT6gMZ+0a4LyPMsBMSIp3knPAviVZZsIr0ZCmYCdrJKKKBPZ h4uA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version; bh=KYxjoHTv6uKj3n82G+0SsQK8lIYz9oQYev2/3hv38x8=; b=X0aHyTxHr151m9dRzp07/wLNjFNps6HQOzs4ECRTE3nY31x2BBuFtEiIhjx6xhfNrm tRNB2Kffqwk3A8to9SFMq/D8xxKLdlC6v0QjAKCyroT3fEv09TNiRhwew7lcgK0C73x4 cbMT50Hm+2TJtiDIpd4xDPrGVe6VmsKOv0gUexHQHVJpdaXbwLZAguG/T8nIPJLAUdX+ rdKDETr1tjQ6aiNczsIGsuE/W4bLl/Qb+KhP9o91/kzK99zmH0N4QkPpnYd3ugwIYLcb 1gWa019QxicYivXPZI9ZBTwY60D79jbC8WTMxAstXpO4lmkcvYM9dLecNwz7TxnaYYE0 Wtcg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d14si10348477eje.95.2020.07.20.03.04.38; Mon, 20 Jul 2020 03:05:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728425AbgGTKBU (ORCPT + 99 others); Mon, 20 Jul 2020 06:01:20 -0400 Received: from mail-io1-f66.google.com ([209.85.166.66]:34354 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728310AbgGTKBT (ORCPT ); Mon, 20 Jul 2020 06:01:19 -0400 Received: by mail-io1-f66.google.com with SMTP id q74so16979572iod.1; Mon, 20 Jul 2020 03:01:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=KYxjoHTv6uKj3n82G+0SsQK8lIYz9oQYev2/3hv38x8=; b=l1A9RaESSIv9LCpOJcjB+lYwQoR48Iyyp8lTYOEmofQn76sU46CBTgW6LI9mRv8tFM z943HuHltQ520CuiVkALpTpnABK40jg9+HD2U4b7vrYXl4g9x9fbbNCtP9k3/2FzY9ry 05GSlwxYopmXxqtIwGR7P6ib0nEKGg86SLCPs4Vee44FITghccbaIu+HiZxxpUI+Cokl kpU/n51Jwrug/TYUuHdO0uAgAz4cmStZcYN1llsBCE4ZEwrmKTZeqfFfxcZvQorwvYE1 TP0Wdk4rOwphPiLb4C62jf5ykyw8x4nXiSox9YtRHuDazqc1Q894oRJu0/XTQOM4rsxr 7uAg== X-Gm-Message-State: AOAM530Z7g+UGrMNG0ipo7qKO3tNcGvxU6FNYqavrPcnlyPBqXShIGuZ wtiqnL/0P3Qa6a5hsy5xZ5jgtDk+u1dY3g2DjzY= X-Received: by 2002:a5d:97d9:: with SMTP id k25mr22200787ios.42.1595239278579; Mon, 20 Jul 2020 03:01:18 -0700 (PDT) MIME-Version: 1.0 References: <20200720074249.596364-1-jiaxun.yang@flygoat.com> <20200720074249.596364-3-jiaxun.yang@flygoat.com> In-Reply-To: <20200720074249.596364-3-jiaxun.yang@flygoat.com> From: Huacai Chen Date: Mon, 20 Jul 2020 18:01:07 +0800 Message-ID: Subject: Re: [PATCH 2/5] MIPS: Loongson64: Process ISA Node in DeviceTree To: Jiaxun Yang Cc: "open list:MIPS" , Rob Herring , Thomas Bogendoerfer , Frank Rowand , Paul Burton , Nathan Chancellor , Nick Desaulniers , devicetree@vger.kernel.org, LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Jiaxun, On Mon, Jul 20, 2020 at 3:44 PM Jiaxun Yang wrote: > > Previously, we're hardcoding resserved ISA I/O Space in code, now > we're processing reverved I/O via DeviceTree directly. Using the ranges > property to determine the size and address of reserved I/O space. Maybe it is better to reserve a default legacy io range if there is no "isa" node in the .dts file? Huacai > > Signed-off-by: Jiaxun Yang > --- > arch/mips/loongson64/init.c | 85 ++++++++++++++++++++++++++----------- > 1 file changed, 60 insertions(+), 25 deletions(-) > > diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c > index 59ddadace83f..028d7b324ec2 100644 > --- a/arch/mips/loongson64/init.c > +++ b/arch/mips/loongson64/init.c > @@ -7,6 +7,8 @@ > #include > #include > #include > +#include > +#include > #include > #include > #include > @@ -63,41 +65,74 @@ void __init prom_free_prom_memory(void) > { > } > > -static __init void reserve_pio_range(void) > +static int __init add_legacy_isa_io(struct fwnode_handle *fwnode, phys_addr_t addr, > + resource_size_t size) > { > + int ret = 0; > struct logic_pio_hwaddr *range; > + unsigned long vaddr; > > range = kzalloc(sizeof(*range), GFP_ATOMIC); > if (!range) > - return; > + return -ENOMEM; > > - range->fwnode = &of_root->fwnode; > - range->size = MMIO_LOWER_RESERVED; > - range->hw_start = LOONGSON_PCIIO_BASE; > + range->fwnode = fwnode; > + range->size = size; > + range->hw_start = addr; > range->flags = LOGIC_PIO_CPU_MMIO; > > - if (logic_pio_register_range(range)) { > - pr_err("Failed to reserve PIO range for legacy ISA\n"); > - goto free_range; > + ret = logic_pio_register_range(range); > + if (ret) { > + kfree(range); > + return ret; > + } > + > + /* Legacy ISA must placed at the start of PCI_IOBASE */ > + if (range->io_start != 0) { > + logic_pio_unregister_range(range); > + kfree(range); > + return -EINVAL; > } > > - if (WARN(range->io_start != 0, > - "Reserved PIO range does not start from 0\n")) > - goto unregister; > - > - /* > - * i8259 would access I/O space, so mapping must be done here. > - * Please remove it when all drivers can be managed by logic_pio. > - */ > - ioremap_page_range(PCI_IOBASE, PCI_IOBASE + MMIO_LOWER_RESERVED, > - LOONGSON_PCIIO_BASE, > - pgprot_device(PAGE_KERNEL)); > - > - return; > -unregister: > - logic_pio_unregister_range(range); > -free_range: > - kfree(range); > + vaddr = PCI_IOBASE + range->io_start; > + > + ioremap_page_range(vaddr, vaddr + size, addr, pgprot_device(PAGE_KERNEL)); > + > + return 0; > +} > + > +static __init void reserve_pio_range(void) > +{ > + struct device_node *np; > + > + for_each_node_by_name(np, "isa") { > + struct of_pci_range range; > + struct of_pci_range_parser parser; > + > + pr_info("ISA Bridge: %pOF\n", np); > + > + if (of_pci_range_parser_init(&parser, np)) { > + pr_info("Failed to parse resources.\n"); > + break; > + } > + > + for_each_of_pci_range(&parser, &range) { > + switch (range.flags & IORESOURCE_TYPE_BITS) { > + case IORESOURCE_IO: > + pr_info(" IO 0x%016llx..0x%016llx\n", > + range.cpu_addr, > + range.cpu_addr + range.size - 1); > + if (add_legacy_isa_io(&np->fwnode, range.cpu_addr, range.size)) > + pr_warn("Failed to reserve legacy IO in Logic PIO\n"); > + break; > + case IORESOURCE_MEM: > + pr_info(" MEM 0x%016llx..0x%016llx\n", > + range.cpu_addr, > + range.cpu_addr + range.size - 1); > + break; > + } > + } > + } > } > > void __init arch_init_irq(void) > -- > 2.28.0.rc1 >