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Tue, 21 Jul 2020 16:25:05 +0000 Date: Tue, 21 Jul 2020 13:25:01 -0300 From: Jason Gunthorpe To: Dave Jiang Cc: vkoul@kernel.org, megha.dey@intel.com, maz@kernel.org, bhelgaas@google.com, rafael@kernel.org, gregkh@linuxfoundation.org, tglx@linutronix.de, hpa@zytor.com, alex.williamson@redhat.com, jacob.jun.pan@intel.com, ashok.raj@intel.com, yi.l.liu@intel.com, baolu.lu@intel.com, kevin.tian@intel.com, sanjay.k.kumar@intel.com, tony.luck@intel.com, jing.lin@intel.com, dan.j.williams@intel.com, kwankhede@nvidia.com, eric.auger@redhat.com, parav@mellanox.com, dave.hansen@intel.com, netanelg@mellanox.com, shahafs@mellanox.com, yan.y.zhao@linux.intel.com, pbonzini@redhat.com, samuel.ortiz@intel.com, mona.hossain@intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, linux-pci@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH RFC v2 04/18] irq/dev-msi: Introduce APIs to allocate/free dev-msi interrupts Message-ID: <20200721162501.GC2021248@mellanox.com> References: <159534667974.28840.2045034360240786644.stgit@djiang5-desk3.ch.intel.com> <159534736176.28840.5547007059232964457.stgit@djiang5-desk3.ch.intel.com> Content-Type: text/plain; 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X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tvd7/H5c/IytsPIVME8EwHSiMLoAbjf2suVvYSgsrIgnMidYYTJoqcBAB/4EgORSUjtscraVTWy2EDkVTukggcFehxc828p1JsbGAsid+hf6I0dVMEOxSyQmjbWY4/WouiOR3EYkBhIgOZIhLh7vjMRLz1UzgYMGgTUcYzgoxy8cr8tM/JY0cnxHK0KtlFLzSHaWp5bsCLQbH35i9PtUZaQ7ZczSXyCC9EpUtqhRUKmspK3kyNuSlFmIG9CmOvVa8DIAhPpPkQHZeBq8sASfmI0o6D2+WEM4Tan/pcF3R4reTsVAcyc7aaisxZAIXcOY4NcV2Z9RBSHK4iiAPlr4mg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR05MB4141.eurprd05.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(4636009)(136003)(346002)(366004)(396003)(376002)(39830400003)(36756003)(86362001)(5660300002)(2906002)(316002)(478600001)(66556008)(66476007)(26005)(426003)(33656002)(6916009)(186003)(8676002)(4326008)(7406005)(83380400001)(7416002)(2616005)(4744005)(9746002)(9786002)(8936002)(66946007)(1076003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: enjRqkU2/KEOmfS0ROVqzO0KNOcuClQIMccQKnBdV4ptmnV6E7illlW2Pu43JGQezIiJ5do/MwxxIKA05D6tYov5qm1MskkjR09pFJi3U+iO2MGCKytzI5IQPDaa4vnTFACO8dWBO4vk+b3JmG86sUHG9UDGxqMqT7CG+YwXwv1cWVlGQzjCAai+0xkAjW0/dsLlW/TTQWD9K221H8qjrMDasY44VHiM9Ibva3y/Bog6BP1FSmSUDRBeJOZdZfn156aaLFY/KZ6foEUGdMmlb70gi3w/TBWCaogbiI+w0ydGZ+3Rfm5hYlGqE0gljaEED6D+o2ZsRW7j/RUgBjlmn+layVgIbHrYrv9KuM7XjcBgL6Cj/oU+EeBAW73snjol4fidbN8R14vbAgu0kQn70iNo+MM1dPyXZdL+7+NWvBcuTKEhPAw7qj8yinG7oikYOHaFP92T2p0iybw7Xls1U8xlVfHnnOMv/TxImazZy/g= X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 15196007-01a4-4df4-f3d3-08d82d92a02c X-MS-Exchange-CrossTenant-AuthSource: VI1PR05MB4141.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2020 16:25:05.0859 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WwFLbMYHvWy1dfO8Lt39VNdX8PiVBAlxyfsca9pDMeY7oklJQU2zKDi124nWKHWpyw7YeUXwVur4r9BaLTkh6A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0502MB3952 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 21, 2020 at 09:02:41AM -0700, Dave Jiang wrote: > From: Megha Dey > > The dev-msi interrupts are to be allocated/freed only for custom devices, > not standard PCI-MSIX devices. > > These interrupts are device-defined and they are distinct from the already > existing msi interrupts: > pci-msi: Standard PCI MSI/MSI-X setup format > platform-msi: Platform custom, but device-driver opaque MSI setup/control > arch-msi: fallback for devices not assigned to the generic PCI domain > dev-msi: device defined IRQ domain for ancillary devices. For e.g. DSA > portal devices use device specific IMS(Interrupt message store) interrupts. > > dev-msi interrupts are represented by their own device-type. That means > dev->msi_list is never contended for different interrupt types. It > will either be all PCI-MSI or all device-defined. Not sure I follow this, where is the enforcement that only dev-msi or normal MSI is being used at one time on a single struct device? Jason