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[71.197.186.152]) by smtp.gmail.com with ESMTPSA id y7sm4130549pjy.54.2020.07.21.14.14.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2020 14:14:51 -0700 (PDT) From: Kevin Hilman To: linux-amlogic@lists.infradead.org, Martin Blumenstingl Cc: narmstrong@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 0/3] GPU DVFS for Meson GXBB/GXL/GXM/G12A/G12B/SM1 Date: Tue, 21 Jul 2020 14:14:46 -0700 Message-Id: <159536607960.30777.14967661305847327487.b4-ty@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200719173213.639540-1-martin.blumenstingl@googlemail.com> References: <20200719173213.639540-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 19 Jul 2020 19:32:10 +0200, Martin Blumenstingl wrote: > Now that we have GPU DVFS support in lima [0] (in Linux 5.7) and > panfrost we can make it work on Amlogic SoCs. > > I decided to remove code duplication for the Mali-450 GPU on GXBB and > GXL so it will be easier to maintain this. This refactoring is part of > patch #1. Patches #2 (GXM) and #3 (G12A, G12B, SM1) are straight > forward; it replaces the hardcoded clock settings with the the GPU OPP > table. > > [...] Applied, thanks! [1/3] arm64: dts: amlogic: meson-gx: add the Mali-450 OPP table and use DVFS commit: 46ffadc7e658277d7559899d7f641f14a3cfae8c [2/3] arm64: dts: amlogic: meson-gxm: add the Mali OPP table and use DVFS commit: 8f16cfabbc0a6c52b114eca2ff8e95bb07949741 [3/3] arm64: dts: amlogic: meson-g12: add the Mali OPP table and use DVFS commit: 916a0edc43f03f86b13fbc9943e5dc936671ea6e Best regards, -- Kevin Hilman