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Date:   Tue, 21 Jul 2020 19:59:00 -0700 (PDT)
Subject:     Re: [PATCH 2/2] riscv: Simplify the checking for SR_PP
In-Reply-To: <4bac52941700cd7b714a41606df7b53f4cf24824.1594629047.git.greentime.hu@sifive.com>
CC:     greentime.hu@sifive.com, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu,
        Paul Walmsley <paul.walmsley@sifive.com>
From:   Palmer Dabbelt <palmer@dabbelt.com>
To:     greentime.hu@sifive.com
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On Mon, 13 Jul 2020 01:32:16 PDT (-0700), greentime.hu@sifive.com wrote:
> This patch simplifies the checking for SR_MPP and SR_SPP. It uses SR_PP in the
> code flow for both m-mode and s-mode then we can remove the ifdef here.
>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>  arch/riscv/kernel/entry.S | 7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 000984695cd6..597beae0d238 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -210,13 +210,8 @@ ret_from_syscall_rejected:
>  ret_from_exception:
>  	REG_L s0, PT_STATUS(sp)
>  	csrc CSR_STATUS, SR_IE
> -#ifdef CONFIG_RISCV_M_MODE
> -	/* the MPP value is too large to be used as an immediate arg for addi */
> -	li t0, SR_MPP
> +	li t0, SR_PP
>  	and s0, s0, t0
> -#else
> -	andi s0, s0, SR_SPP
> -#endif
>  	bnez s0, resume_kernel
>
>  resume_userspace:

This one is actually on a fairly fast path, so I can buy it's worth saving the
cycle.