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Tue, 21 Jul 2020 23:55:35 -0700 Received: from [172.19.3.8] (helo=xsjamitsuni50.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jy8f9-00036T-6D; Tue, 21 Jul 2020 23:55:35 -0700 From: Amit Sunil Dhamne To: mturquette@baylibre.com, m.tretter@pengutronix.de, sboyd@codeaurora.org, sboyd@kernel.org, michal.simek@xilinx.com, mark.rutland@arm.com, linux-clk@vger.kernel.org Cc: rajanv@xilinx.com, jollys@xilinx.com, tejasp@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rajan Vaja , Tejas Patel , Amit Sunil Dhamne Subject: [PATCH v2 2/3] clk: zynqmp: Use firmware specific divider clock flags Date: Tue, 21 Jul 2020 23:55:31 -0700 Message-Id: <1595400932-303612-3-git-send-email-amit.sunil.dhamne@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595400932-303612-1-git-send-email-amit.sunil.dhamne@xilinx.com> References: <1595400932-303612-1-git-send-email-amit.sunil.dhamne@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapsmtpgw01;PTR:unknown-60-83.xilinx.com;CAT:NONE;SFTY:;SFS:(396003)(376002)(136003)(346002)(39860400002)(46966005)(36756003)(2616005)(83380400001)(426003)(26005)(478600001)(5660300002)(356005)(186003)(107886003)(4326008)(81166007)(336012)(82310400002)(8936002)(7696005)(6666004)(9786002)(47076004)(316002)(82740400003)(8676002)(70206006)(70586007)(2906002)(54906003);DIR:OUT;SFP:1101; X-MS-PublicTrafficType: Email MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: b4bae31b-de41-4d07-7757-08d82e0c3fbf X-MS-TrafficTypeDiagnostic: CY4PR02MB2661: X-Microsoft-Antispam-PRVS: Content-Transfer-Encoding: quoted-printable X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:597; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Yt2bK1elrbCIvqbScRp+NCEw7Te4U+W9eoOWG0qTyaXvjZOOtd45wsZKyyYHP+veBYw175Rd3KqgcrYYdRTCNFN9pe8lbVsmiey/zf3ChJmkAwkvGbwtYrNac8Tl9724YVpSnd6DZGPLVzuoXsM6X1ubzKYbqP1kZoC+WnjEnVxGql35Ki19jk8iyNEz4NprhCfbcxqjbfRr/2m0rvCWeTFRrIKJQ4MS2dpKUF5pdlDlEgfADmsFGPnYR2rHeih31lgNS7esGwaIxZpsd4s4CtwiYMGOkfrkOLp7941U0GrFUwngEvMN86DJomRsVdQPxu1xrq7Ykzv22Rcab6maemc/RFNwHgaojqdpd814rSo7njnbVKACkyLd3elDD5QGORTKn7CuvzBSUUmGpZc1zA== X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jul 2020 06:55:41.6790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b4bae31b-de41-4d07-7757-08d82e0c3fbf X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT061.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2661 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Rajan Vaja Use ZynqMP specific divider clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja Signed-off-by: Tejas Patel Signed-off-by: Amit Sunil Dhamne --- drivers/clk/zynqmp/clk-zynqmp.h | 9 +++++++++ drivers/clk/zynqmp/divider.c | 16 +++++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqm= p.h index 3cb6149..ec33525 100644 --- a/drivers/clk/zynqmp/clk-zynqmp.h +++ b/drivers/clk/zynqmp/clk-zynqmp.h @@ -32,6 +32,15 @@ /* do not gate, ever */ #define ZYNQMP_CLK_IS_CRITICAL BIT(11) +/* Type Flags for divider clock */ +#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0) +#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3) +#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4) +#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5) +#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6) + enum topology_type { TYPE_INVALID, TYPE_MUX, diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 3ab57d9..86cb785 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -320,7 +320,21 @@ struct clk_hw *zynqmp_clk_register_divider(const char = *name, /* struct clk_divider assignments */ div->is_frac =3D !!((nodes->flag & CLK_FRAC) | (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC))= ; - div->flags =3D nodes->type_flag; + div->flags =3D 0; + div->flags |=3D (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) ? + CLK_DIVIDER_ONE_BASED : 0; + div->flags |=3D (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO= ) ? + CLK_DIVIDER_POWER_OF_TWO : 0; + div->flags |=3D (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) = ? + CLK_DIVIDER_ALLOW_ZERO : 0; + div->flags |=3D (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO= ) ? + CLK_DIVIDER_HIWORD_MASK : 0; + div->flags |=3D (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSES= T) ? + CLK_DIVIDER_ROUND_CLOSEST : 0; + div->flags |=3D (nodes->type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) ? + CLK_DIVIDER_READ_ONLY : 0; + div->flags |=3D (nodes->type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO)= ? + CLK_DIVIDER_MAX_AT_ZERO : 0; div->hw.init =3D &init; div->clk_id =3D clk_id; div->div_type =3D nodes->type; -- 2.7.4 This email and any attachments are intended for the sole use of the named r= ecipient(s) and contain(s) confidential information that may be proprietary= , privileged or copyrighted under applicable law. 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