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Subject: Re: [PATCH 2/4] i2c: mediatek: Support DMA mask range over 33-bits
To:     Qii Wang <qii.wang@mediatek.com>, wsa@the-dreams.de
Cc:     qiangming.xia@mediatek.com, devicetree@vger.kernel.org,
        srv_heupstream@mediatek.com, leilk.liu@mediatek.com,
        linux-kernel@vger.kernel.org, robh+dt@kernel.org,
        linux-mediatek@lists.infradead.org, linux-i2c@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org
References: <1595421106-10017-1-git-send-email-qii.wang@mediatek.com>
 <1595421106-10017-3-git-send-email-qii.wang@mediatek.com>
From:   Matthias Brugger <matthias.bgg@gmail.com>
Message-ID: <87429327-5d2e-e3f3-db22-04e225a31055@gmail.com>
Date:   Wed, 22 Jul 2020 17:38:26 +0200
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On 22/07/2020 14:31, Qii Wang wrote:
> Replace 'support_33bits with 'dma_max_support' for DMA mask
> operation, and replace 'mtk_i2c_set_4g_mode' with 'upper_32_bits'.

Please explain more in detail what you are doing and how this fits to the way 
the HW works.

> 
> Signed-off-by: Qii Wang <qii.wang@mediatek.com>
> ---
>   drivers/i2c/busses/i2c-mt65xx.c | 37 +++++++++++++++++--------------------
>   1 file changed, 17 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> index e6b984a..e475877 100644
> --- a/drivers/i2c/busses/i2c-mt65xx.c
> +++ b/drivers/i2c/busses/i2c-mt65xx.c
> @@ -209,6 +209,7 @@ struct mtk_i2c_compatible {
>   	unsigned char dma_sync: 1;
>   	unsigned char ltiming_adjust: 1;
>   	unsigned char apdma_sync: 1;
> +	unsigned char max_dma_support;
>   };
>   
>   struct mtk_i2c_ac_timing {
> @@ -311,11 +312,11 @@ struct i2c_spec_values {
>   	.dcm = 1,
>   	.auto_restart = 1,
>   	.aux_len_reg = 1,
> -	.support_33bits = 1,
>   	.timing_adjust = 1,
>   	.dma_sync = 0,
>   	.ltiming_adjust = 0,
>   	.apdma_sync = 0,
> +	.max_dma_support = 33,
>   };
>   
>   static const struct mtk_i2c_compatible mt6577_compat = {
> @@ -325,11 +326,11 @@ struct i2c_spec_values {
>   	.dcm = 1,
>   	.auto_restart = 0,
>   	.aux_len_reg = 0,
> -	.support_33bits = 0,
>   	.timing_adjust = 0,
>   	.dma_sync = 0,
>   	.ltiming_adjust = 0,
>   	.apdma_sync = 0,
> +	.max_dma_support = 32,
>   };
>   
>   static const struct mtk_i2c_compatible mt6589_compat = {
> @@ -339,11 +340,11 @@ struct i2c_spec_values {
>   	.dcm = 0,
>   	.auto_restart = 0,
>   	.aux_len_reg = 0,
> -	.support_33bits = 0,
>   	.timing_adjust = 0,
>   	.dma_sync = 0,
>   	.ltiming_adjust = 0,
>   	.apdma_sync = 0,
> +	.max_dma_support = 32,
>   };
>   
>   static const struct mtk_i2c_compatible mt7622_compat = {
> @@ -353,11 +354,11 @@ struct i2c_spec_values {
>   	.dcm = 1,
>   	.auto_restart = 1,
>   	.aux_len_reg = 1,
> -	.support_33bits = 0,
>   	.timing_adjust = 0,
>   	.dma_sync = 0,
>   	.ltiming_adjust = 0,
>   	.apdma_sync = 0,
> +	.max_dma_support = 32,
>   };
>   
>   static const struct mtk_i2c_compatible mt8173_compat = {
> @@ -366,11 +367,11 @@ struct i2c_spec_values {
>   	.dcm = 1,
>   	.auto_restart = 1,
>   	.aux_len_reg = 1,
> -	.support_33bits = 1,
>   	.timing_adjust = 0,
>   	.dma_sync = 0,
>   	.ltiming_adjust = 0,
>   	.apdma_sync = 0,
> +	.max_dma_support = 33,
>   };
>   
>   static const struct mtk_i2c_compatible mt8183_compat = {
> @@ -380,11 +381,11 @@ struct i2c_spec_values {
>   	.dcm = 0,
>   	.auto_restart = 1,
>   	.aux_len_reg = 1,
> -	.support_33bits = 1,
>   	.timing_adjust = 1,
>   	.dma_sync = 1,
>   	.ltiming_adjust = 1,
>   	.apdma_sync = 0,
> +	.max_dma_support = 33,
>   };
>   
>   static const struct of_device_id mtk_i2c_of_match[] = {
> @@ -796,11 +797,6 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
>   	return 0;
>   }
>   
> -static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
> -{
> -	return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;

I2C_DMA_4G_MODE define could now be deleted as well.

Regards,
Matthias

> -}
> -
>   static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
>   			       int num, int left_num)
>   {
> @@ -885,8 +881,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
>   			return -ENOMEM;
>   		}
>   
> -		if (i2c->dev_comp->support_33bits) {
> -			reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
> +		if (i2c->dev_comp->max_dma_support > 32) {
> +			reg_4g_mode = upper_32_bits(rpaddr);
>   			writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
>   		}
>   
> @@ -908,8 +904,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
>   			return -ENOMEM;
>   		}
>   
> -		if (i2c->dev_comp->support_33bits) {
> -			reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
> +		if (i2c->dev_comp->max_dma_support > 32) {
> +			reg_4g_mode = upper_32_bits(wpaddr);
>   			writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
>   		}
>   
> @@ -954,11 +950,11 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
>   			return -ENOMEM;
>   		}
>   
> -		if (i2c->dev_comp->support_33bits) {
> -			reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
> +		if (i2c->dev_comp->max_dma_support > 32) {
> +			reg_4g_mode = upper_32_bits(wpaddr);
>   			writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
>   
> -			reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
> +			reg_4g_mode = upper_32_bits(rpaddr);
>   			writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
>   		}
>   
> @@ -1232,8 +1228,9 @@ static int mtk_i2c_probe(struct platform_device *pdev)
>   		return -EINVAL;
>   	}
>   
> -	if (i2c->dev_comp->support_33bits) {
> -		ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
> +	if (i2c->dev_comp->max_dma_support > 32) {
> +		ret = dma_set_mask(&pdev->dev,
> +				DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
>   		if (ret) {
>   			dev_err(&pdev->dev, "dma_set_mask return error.\n");
>   			return ret;
>