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Wed, 22 Jul 2020 16:40:04 +0000 Subject: Re: [PATCH] mtd: spi-nor: intel-spi: Simulate WRDI command To: Tudor.Ambarus@microchip.com, mika.westerberg@linux.intel.com Cc: vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, ibr@ilbers.de References: <282e1305-fd08-e446-1a22-eb4dff78cfb4@nokia.com> <20200722143604.GQ5180@lahna.fi.intel.com> <99e3f6c7-e9a6-584c-883a-0882f5137b7b@microchip.com> From: Alexander Sverdlin Message-ID: <19cd6fb0-1fd0-2a2e-2612-5a5bc159386a@nokia.com> Date: Wed, 22 Jul 2020 18:40:00 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 In-Reply-To: <99e3f6c7-e9a6-584c-883a-0882f5137b7b@microchip.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: HE1PR0202CA0002.eurprd02.prod.outlook.com (2603:10a6:3:8c::12) To HE1PR07MB4412.eurprd07.prod.outlook.com (2603:10a6:7:96::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ulegcpsvhp1.emea.nsn-net.net (131.228.32.167) by HE1PR0202CA0002.eurprd02.prod.outlook.com (2603:10a6:3:8c::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3216.21 via Frontend Transport; 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On 22/07/2020 17:18, Tudor.Ambarus@microchip.com wrote: [...] >>>> After spi_nor_write_disable() return code checks were introduced in the >>>> spi-nor front end intel-spi backend stopped to work because WRDI was never >>>> supported and always failed. >>>> >>>> Just pretend it was sucessful and ignore the command itself. HW sequencer >>>> shall do the right thing automatically, while with SW sequencer we cannot >>>> do it anyway, because the only tool we had was preopcode and it makes no >>>> sense for WRDI. >>>> >>>> Cc: stable@vger.kernel.org >>>> Fixes: bce679e5ae3a ("mtd: spi-nor: Check for errors after each Register Operation") >>>> Signed-off-by: Alexander Sverdlin >>>> --- >>>> drivers/mtd/spi-nor/controllers/intel-spi.c | 8 ++++++++ >>>> 1 file changed, 8 insertions(+) >>>> >>>> diff --git a/drivers/mtd/spi-nor/controllers/intel-spi.c b/drivers/mtd/spi-nor/controllers/intel-spi.c >>>> index 61d2a0a..134b356 100644 >>>> --- a/drivers/mtd/spi-nor/controllers/intel-spi.c >>>> +++ b/drivers/mtd/spi-nor/controllers/intel-spi.c >>>> @@ -612,6 +612,14 @@ static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf, >>>> return 0; >>>> } >>>> >>>> + /* >>>> + * We hope that HW sequencer will do the right thing automatically and >>>> + * with the SW seuencer we cannot use preopcode any way, so just ignore >> ^^^^^^^^ >> Typo, should be sequencer. >> >> Otherwise looks good to me. >> > It looks good to me too. Should I add your R-b tag when applying? > I can fix the typo. Thank you, Mika, Tudor! -- Best regards, Alexander Sverdlin.