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From:   Thomas Gleixner <tglx@linutronix.de>
To:     Ricardo Neri <ricardo.neri-calderon@linux.intel.com>,
        Andy Lutomirski <luto@kernel.org>
Cc:     Cathy Zhang <cathy.zhang@intel.com>,
        kvm list <kvm@vger.kernel.org>,
        LKML <linux-kernel@vger.kernel.org>, X86 ML <x86@kernel.org>,
        Paolo Bonzini <pbonzini@redhat.com>,
        "Christopherson\, Sean J" <sean.j.christopherson@intel.com>,
        Vitaly Kuznetsov <vkuznets@redhat.com>,
        Wanpeng Li <wanpengli@tencent.com>,
        Jim Mattson <jmattson@google.com>,
        Joerg Roedel <joro@8bytes.org>, Ingo Molnar <mingo@redhat.com>,
        Borislav Petkov <bp@alien8.de>,
        "H. Peter Anvin" <hpa@zytor.com>,
        Kyung Min Park <kyung.min.park@intel.com>,
        Josh Poimboeuf <jpoimboe@redhat.com>,
        Greg KH <gregkh@linuxfoundation.org>,
        Andi Kleen <ak@linux.intel.com>,
        Dave Hansen <dave.hansen@intel.com>,
        Tony Luck <tony.luck@intel.com>,
        "Ravi V. Shankar" <ravi.v.shankar@intel.com>, fenghua.yu@intel.com
Subject: Re: [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction
In-Reply-To: <20200708022102.GA25016@ranerica-svr.sc.intel.com>
References: <1594088183-7187-1-git-send-email-cathy.zhang@intel.com> <1594088183-7187-2-git-send-email-cathy.zhang@intel.com> <CALCETrWudiF8G8r57r5i4JefuP5biG1kHg==0O8YXb-bYS-0BA@mail.gmail.com> <20200708022102.GA25016@ranerica-svr.sc.intel.com>
Date:   Thu, 23 Jul 2020 01:02:43 +0200
Message-ID: <87eep3ywz0.fsf@nanos.tec.linutronix.de>
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Ricardo Neri <ricardo.neri-calderon@linux.intel.com> writes:
> On Tue, Jul 07, 2020 at 09:36:15AM -0700, Andy Lutomirski wrote:
>> On Mon, Jul 6, 2020 at 7:21 PM Cathy Zhang <cathy.zhang@intel.com> wrote:
>> >
>> > This instruction gives software a way to force the processor to complete
>> > all modifications to flags, registers and memory from previous instructions
>> > and drain all buffered writes to memory before the next instruction is
>> > fetched and executed.
>> >
>> > The same effect can be obtained using the cpuid instruction. However,
>> > cpuid causes modification on the eax, ebx, ecx, and ecx regiters; it
>> > also causes a VM exit.
>> >
>> > A processor supports SERIALIZE instruction if CPUID.0x0x.0x0:EDX[14] is
>> > present. The CPU feature flag is shown as "serialize" in /proc/cpuinfo.
>> >
>> > Detailed information on the instructions and CPUID feature flag SERIALIZE
>> > can be found in the latest Intel Architecture Instruction Set Extensions
>> > and Future Features Programming Reference and Intel 64 and IA-32
>> > Architectures Software Developer's Manual.
>> 
>> Can you also wire this up so sync_core() uses it?
>
> I am cc'ing Fenghua, who has volunteered to work on this. Addind support
> for SERIALIZE in sync_core() should not block merging these patches,
> correct?

Come on. We are not serving KVM first before making this usable on bare
metal.

Thanks,

        tglx