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([2a01:e34:ed2f:f020:dca7:8d30:33fa:daac]) by smtp.googlemail.com with ESMTPSA id b8sm3980634wrv.4.2020.07.23.07.34.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Jul 2020 07:34:08 -0700 (PDT) Subject: Re: [PATCH v5 2/4] clocksource/drivers: Add CLINT timer driver To: Anup Patel , Palmer Dabbelt , Paul Walmsley , Albert Ou , Rob Herring , Thomas Gleixner Cc: Damien Le Moal , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Emil Renner Berhing References: <20200723142409.47057-1-anup.patel@wdc.com> <20200723142409.47057-3-anup.patel@wdc.com> From: Daniel Lezcano Message-ID: Date: Thu, 23 Jul 2020 16:34:07 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200723142409.47057-3-anup.patel@wdc.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/07/2020 16:24, Anup Patel wrote: > We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e. > RISC-V NoMMU kernel). > > The CLINT MMIO device provides three things: > 1. 64bit free running counter register > 2. 64bit per-CPU time compare registers > 3. 32bit per-CPU inter-processor interrupt registers > > Unlike other timer devices, CLINT provides IPI registers along with > timer registers. To use CLINT IPI registers, the CLINT timer driver > provides IPI related callbacks to arch/riscv. > > Signed-off-by: Anup Patel > Tested-by: Emil Renner Berhing > --- Acked-by: Daniel Lezcano -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog