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Date:   Thu, 23 Jul 2020 18:54:48 +0200
From:   Maxime Ripard <maxime@cerno.tech>
To:     Frank Lee <frank@allwinnertech.com>
Cc:     robh+dt@kernel.org, wens@csie.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        tiny.windzz@gmail.com, huangshuosheng@allwinnertech.com,
        liyong@allwinnertech.com
Subject: Re: [PATCH v4 14/16] arm64: allwinner: A100: add the basical
 Allwinner A100 DTSI file
Message-ID: <20200723165448.crdc4fc5jwqmsret@gilmour.lan>
References: <cover.1594708863.git.frank@allwinnertech.com>
 <f7f86c648bad6e72f8fc8117b96065bf5326a273.1594708864.git.frank@allwinnertech.com>
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Hi,

On Tue, Jul 14, 2020 at 03:20:29PM +0800, Frank Lee wrote:
> From: Yangtao Li <frank@allwinnertech.com>
>=20
> Allwinner A100 is a new SoC with Cortex-A53 cores, this commit adds
> the basical DTSI file of it, including the clock, i2c, pins, sid, ths,
> nmi, and UART support.
>=20
> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
> ---
>  .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 ++++++++++++++++++
>  1 file changed, 364 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>=20
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/=
boot/dts/allwinner/sun50i-a100.dtsi
> new file mode 100644
> index 000000000000..3fb2443f2121
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -0,0 +1,364 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/sun50i-a100-ccu.h>
> +#include <dt-bindings/clock/sun50i-a100-r-ccu.h>
> +#include <dt-bindings/reset/sun50i-a100-ccu.h>
> +#include <dt-bindings/reset/sun50i-a100-r-ccu.h>
> +
> +/ {
> +	interrupt-parent =3D <&gic>;
> +	#address-cells =3D <2>;
> +	#size-cells =3D <2>;
> +
> +	cpus {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible =3D "arm,armv8";

You should use the arm,cortex-a53 compatible here, arm,armv8 is for
software models.

> +		sid@3006000 {

The node name is supposed to be the class of the device, and the DT spec
defines a list of them already. eeprom would be better suited here.

> +	thermal-zones {
> +		cpu-thermal-zone {
> +			polling-delay-passive =3D <0>;
> +			polling-delay =3D <0>;
> +			thermal-sensors =3D <&ths 0>;
> +		};
> +
> +		gpu-thermal-zone {
> +			polling-delay-passive =3D <0>;
> +			polling-delay =3D <0>;
> +			thermal-sensors =3D <&ths 1>;
> +		};
> +
> +		ddr-thermal-zone {
> +			polling-delay-passive =3D <0>;
> +			polling-delay =3D <0>;
> +			thermal-sensors =3D <&ths 2>;
> +		};
> +	};

Ideally, the nodes here should be ordered by alphabetical order (so ddr
before GPU).

Thanks!
Maxime