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To:     Alex Deucher <alexdeucher@gmail.com>
Cc:     Bjorn Helgaas <helgaas@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Linux PCI <linux-pci@vger.kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        =?UTF-8?Q?Christian_K=c3=b6nig?= <christian.koenig@amd.com>,
        Huang Rui <ray.huang@amd.com>,
        Andrew Maier <andrew.maier@eideticom.com>,
        "H. Peter Anvin" <hpa@zytor.com>
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From:   Logan Gunthorpe <logang@deltatee.com>
Message-ID: <7d013200-3257-9f91-cace-4c43947a7f78@deltatee.com>
Date:   Thu, 23 Jul 2020 14:45:37 -0600
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Subject: Re: [PATCH] PCI/P2PDMA: Add AMD Zen 2 root complex to the list of
 allowed bridges
Sender: linux-kernel-owner@vger.kernel.org
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On 2020-07-23 2:18 p.m., Alex Deucher wrote:
> On Thu, Jul 23, 2020 at 4:11 PM Logan Gunthorpe <logang@deltatee.com> wrote:
>>
>>
>>
>> On 2020-07-23 1:57 p.m., Bjorn Helgaas wrote:
>>> [+cc Andrew, Armen, hpa]
>>>
>>> On Thu, Jul 23, 2020 at 02:01:17PM -0400, Alex Deucher wrote:
>>>> On Thu, Jul 23, 2020 at 1:43 PM Logan Gunthorpe <logang@deltatee.com> wrote:
>>>>>
>>>>> The AMD Zen 2 root complex (Starship/Matisse) was tested for P2PDMA
>>>>> transactions between root ports and found to work. Therefore add it
>>>>> to the list.
>>>>>
>>>>> Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
>>>>> Cc: Bjorn Helgaas <bhelgaas@google.com>
>>>>> Cc: Christian König <christian.koenig@amd.com>
>>>>> Cc: Huang Rui <ray.huang@amd.com>
>>>>> Cc: Alex Deucher <alexdeucher@gmail.com>
>>>>
>>>> Starting with Zen, all AMD platforms support P2P for reads and writes.
>>>
>>> What's the plan for getting out of the cycle of "update this list for
>>> every new chip"?  Any new _DSMs planned, for instance?
>>
>> Well there was an effort to add capabilities in the PCI spec to describe
>> this but, as far as I know, they never got anywhere, and hardware still
>> doesn't self describe with this.
>>
>>> A continuous trickle of updates like this is not really appealing.  So
>>> far we have:
>>>
>>>   7d5b10fcb81e ("PCI/P2PDMA: Add AMD Zen Raven and Renoir Root Ports to whitelist")
>>>   7b94b53db34f ("PCI/P2PDMA: Add Intel Sky Lake-E Root Ports B, C, D to the whitelist")
>>>   bc123a515cb7 ("PCI/P2PDMA: Add Intel SkyLake-E to the whitelist")
>>>   494d63b0d5d0 ("PCI/P2PDMA: Whitelist some Intel host bridges")
>>>   0f97da831026 ("PCI/P2PDMA: Allow P2P DMA between any devices under AMD ZEN Root Complex")
>>>
>>> And that's just from the last year, not including this patch.
>>
>> Yes, it's not ideal. But most of these are adding old devices as people
>> test and care about running on those platforms -- a lot of this is
>> bootstrapping the list. I'd expect this to slow down a bit as by now we
>> have hopefully got a lot of the existing platforms people care about.
>> But we'd still probably expect to be adding a new Intel and AMD devices
>> about once a year as they produce new hardware designs.
>>
>> Unless, the Intel and AMD folks know of a way to detect this, or even to
>> query if a root complex is newer than a certain generation, I'm not sure
>> what else we can do here.
> 
> I started a thread internally to see if I can find a way.  FWIW,
> pre-ZEN parts also support p2p DMA, but only for writes.  If I can get
> a definitive list, maybe we could switch to a blacklist for the old
> ones?

It would have to be an AMD specific list, falling back to the general
whitelist.... I suppose we can also mine the pci_ids database for Intel
root complexes and create a blacklist there too. But there are a lot
more root complexes outside of the x86 world...

Logan