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Date:   Mon, 27 Jul 2020 10:20:24 +0100
From:   Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To:     Logan Gunthorpe <logang@deltatee.com>
CC:     Bjorn Helgaas <helgaas@kernel.org>,
        Alex Deucher <alexdeucher@gmail.com>,
        LKML <linux-kernel@vger.kernel.org>,
        Linux PCI <linux-pci@vger.kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Christian =?ISO-8859-1?Q?K=F6nig?= <christian.koenig@amd.com>,
        Huang Rui <ray.huang@amd.com>,
        Andrew Maier <andrew.maier@eideticom.com>,
        "H. Peter Anvin" <hpa@zytor.com>,
        Eric Wehage <Eric.Wehage@futurewei.com>,
        "Alex Umansky" <alex.umansky@huawei.com>
Subject: Re: [PATCH] PCI/P2PDMA: Add AMD Zen 2 root complex to the list of
 allowed bridges
Message-ID: <20200727102024.00005f8b@Huawei.com>
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References: <20200724150641.GA1518875@bjorn-Precision-5520>
        <59b68da4-cd3c-bf65-6654-02d4feaede27@deltatee.com>
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On Fri, 24 Jul 2020 09:56:39 -0600
Logan Gunthorpe <logang@deltatee.com> wrote:

> [+cc Jonathan]
> 
> On 2020-07-24 9:06 a.m., Bjorn Helgaas wrote:
> > On Thu, Jul 23, 2020 at 02:10:52PM -0600, Logan Gunthorpe wrote:  
> >> On 2020-07-23 1:57 p.m., Bjorn Helgaas wrote:  
> >>> On Thu, Jul 23, 2020 at 02:01:17PM -0400, Alex Deucher wrote:  
> >>>> On Thu, Jul 23, 2020 at 1:43 PM Logan Gunthorpe <logang@deltatee.com> wrote:  
> >>>>>
> >>>>> The AMD Zen 2 root complex (Starship/Matisse) was tested for P2PDMA
> >>>>> transactions between root ports and found to work. Therefore add it
> >>>>> to the list.
> >>>>>
> >>>>> Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
> >>>>> Cc: Bjorn Helgaas <bhelgaas@google.com>
> >>>>> Cc: Christian K?nig <christian.koenig@amd.com>
> >>>>> Cc: Huang Rui <ray.huang@amd.com>
> >>>>> Cc: Alex Deucher <alexdeucher@gmail.com>  
> >>>>
> >>>> Starting with Zen, all AMD platforms support P2P for reads and writes.  
> >>>
> >>> What's the plan for getting out of the cycle of "update this list for
> >>> every new chip"?  Any new _DSMs planned, for instance?  
> >>
> >> Well there was an effort to add capabilities in the PCI spec to describe
> >> this but, as far as I know, they never got anywhere, and hardware still
> >> doesn't self describe with this.  
> > 
> > Any idea what happened?  Is there hope for the future?  I'm really not
> > happy about signing up for open-ended device-specific patches like
> > this.  It's certainly not in the plug and play spirit that has made
> > PCI successful.  I know, preaching to the choir here.  
> 
> Agreed, though I'm not really hooked into the PCI SIG. The last email I
> got about this was an RFC from Jonathan Cameron in late 2018. I've CC'd
> him here, maybe he'll have a bit more insight.

For non technical reasons, you can probably figure out, that particular
ECR stalled. Unfortunately I can't directly provide info on any newer
discussions. Eric, could you perhaps find out if there is anything we can share?

This is the same question of trying to find a way to avoid white listing
root complexes that can do peer 2 peer that would have been covered by
your Advanced Peer to Peer Capabilities ECR.

Thanks,

Jonathan


> 
> Logan